Zhongfeng Wang

发表

Reduced Complexity K-Best Sphere Decoder Design for MIMO Systems

Qingwei Li, Zhongfeng Wang, 2008 .

An Efficient Accelerator of the Squaring for the Verifiable Delay Function Over a Class Group

Zhongfeng Wang, Danyang Zhu, Yifeng Song, 2020, 2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

AN ABSTRACT OF THE THESIS OF Lupin Chen for the degree of Master of Science in Electrical and Computer Engineering presented on September 4, 2007. Title: Modified VLSI Designs for Error Correction Codes

Huaping Liu, J. Coakley, A. Thesis, 2007 .

An Efficient VLSI Architecture for

Zhongfeng Wang, Jun Lin, Jin Sha, 2010 .

Low-complexity sphere decoding for MIMO-SCMA systems

Chaojing Tang, Jing Lei, Lei Wen, 2021, IET Commun..

A Three-Level Scoring System for Fast Similarity Evaluation Based on Smith-Waterman Algorithm

Zhongfeng Wang, Jiajun Wu, Jun Lin, 2020, 2020 IEEE International Symposium on Circuits and Systems (ISCAS).

Dynamical Textures Modeling via Joint Video Dictionary Learning

Hao Shen, M. Kleinsteuber, Zhongfeng Wang, 2017, IEEE Transactions on Image Processing.

RVDFI: A RISC-V Architecture with Security Enforcement by High Performance Complete Data-Flow Integrity

Zhongfeng Wang, Lang Feng, Jiayi Huang, 2021, IEEE Transactions on Computers.

Iterative Hard Thresholding Algorithm-Based Detector for Compressed OFDM-IM Systems

Zhongfeng Wang, B. Hong, Hui Qian, 2022, IEEE Communications Letters.

A Reconfigurable Accelerator for Generative Adversarial Network Training Based on FPGA

Zhongfeng Wang, Tongtong Yin, W. Mao, 2021, 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

A Memory-Efficient Hardware Architecture for Deformable Convolutional Networks

Zhongfeng Wang, Jiapeng Luo, W. Mao, 2021, 2021 IEEE Workshop on Signal Processing Systems (SiPS).

LITNet: A Light-weight Image Transform Net for Image Style Transfer

Zhongfeng Wang, Huihong Shi, W. Mao, 2021, 2021 International Joint Conference on Neural Networks (IJCNN).

Low-latency Hardware Architecture for VDF Evaluation in Class Groups

Zhongfeng Wang, Danyang Zhu, Jing Tian, 2023, IEEE Transactions on Computers.

Fast Permutation Architecture on Encrypted Data for Secure Neural Network Inference

Zhongfeng Wang, Jing Tian, Xiao Hu, 2020, 2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

PipeBSW: A Two-Stage Pipeline Structure for Banded Smith-Waterman Algorithm on FPGA

Zhongfeng Wang, Jun Lin, Luyi Li, 2021, 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

High-Throughput LDPC-CC Decoders Based on Storage, Arithmetic, and Control Improvements

Zhongfeng Wang, Yuxing Chen, Hangxuan Cui, 2022, IEEE Transactions on Circuits and Systems II: Express Briefs.

An Algorithm–Hardware Co-Optimized Framework for Accelerating N:M Sparse Transformers

Aojun Zhou, Zhongfeng Wang, Chao Fang, 2022, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Accelerating NLP Tasks on FPGA with Compressed BERT and a Hardware-Oriented Early Exit Method

Siyuan Lu, Keli Xie, Zhongfeng Wang, 2022, 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

An Efficient Hardware Accelerator for Sparse Transformer Neural Networks

Zhongfeng Wang, Jun Lin, Ming-Kai Hsu, 2022, 2022 IEEE International Symposium on Circuits and Systems (ISCAS).

UCViT: Hardware-Friendly Vision Transformer via Unified Compression

Zhongfeng Wang, Hongrui Song, Ya Wang, 2022, 2022 IEEE International Symposium on Circuits and Systems (ISCAS).

Fast and Accurate FSA System Using ELBERT: An Efficient and Lightweight BERT

Siyuan Lu, Keli Xie, Zhongfeng Wang, 2022, 2211.08842.

High-Speed VLSI Architectures for Turbo Decoders

Zhongfeng Wang, Xinming Huang, Zhongfeng Wang, 2010 .

Low-Latency Design and Implementation of the Squaring in Class Groups for Verifiable Delay Function Using Redundant Representation

Zhongfeng Wang, Danyang Zhu, Jing Tian, 2022, IACR Trans. Cryptogr. Hardw. Embed. Syst..

Efficient Homomorphic Convolution Designs on FPGA for Secure Inference

Zhongfeng Wang, Jing Tian, Minghao Li, 2022, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Deep Neural Network Interlayer Feature Map Compression Based on Least-Squares Fitting

Yuan Du, Xiaoliang Chen, L. Du, 2022, 2022 IEEE International Symposium on Circuits and Systems (ISCAS).

Fast and Accurate FSA System Using ELBERT: An Efficient and Lightweight BERT

Siyuan Lu, Keli Xie, Zhongfeng Wang, 2022, ArXiv.

BEBERT: Efficient and robust binary ensemble BERT

Hong Wang, Zhongfeng Wang, Chao Fang, 2022, 2210.15976.

Wireless Multiferroic Memristor with Coupled Giant Impedance and Artificial Synapse Application

Y. Wen, Ping Li, Zhongfeng Wang, 2022, Advanced Electronic Materials.

NASA: Neural Architecture Search and Acceleration for Hardware Inspired Hybrid Networks

Haoran You, Yingyan Lin, Zhongfeng Wang, 2022, 2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

GANDSE: Generative Adversarial Network-based Design Space Exploration for Neural Network Accelerator Design

Zhongfeng Wang, Ke Tang, Wenjian Liu, 2022, ACM Trans. Design Autom. Electr. Syst..

A Reconfigurable DNN Training Accelerator on FPGA

Zhongfeng Wang, Jun Lin, Jinming Lu, 2020, 2020 IEEE Workshop on Signal Processing Systems (SiPS).

Financial Time Series Forecasting Model Based on EMD and Rolling Grey Model

Zhongfeng Wang, Jun Lin, Binjing Li, 2020, 2020 IEEE Workshop on Signal Processing Systems (SiPS).

FPAP: A Folded Architecture for Energy-Quality Scalable Convolutional Neural Networks

Zhongfeng Wang, Jun Lin, Yizhi Wang, 2019, IEEE Transactions on Circuits and Systems I: Regular Papers.

FPAP: A Folded Architecture for Efficient Computing of Convolutional Neural Networks

Zhongfeng Wang, Yizhi Wang, Jun Lin, 2018, 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

An Energy-Efficient Architecture for Binary Weight Convolutional Neural Networks

Zhongfeng Wang, Jun Lin, Yizhi Wang, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

IEEE Transactions on Circuits and Systems—II:Express Briefs publication information

Mohamad Sawan, Alyssa B. Apsel, Peng Li, 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

Memory-Efficient CNN Accelerator Based on Interlayer Feature Map Compression

Zhongfeng Wang, Xiaoliang Chen, Zhuang Shao, 2021, IEEE Transactions on Circuits and Systems I: Regular Papers.

Flexible-width Bit-level Compressor for Convolutional Neural Network

Li Du, Yuan Du, Zhongfeng Wang, 2021, 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS).

USCA: A Unified Systolic Convolution Array Architecture for Accelerating Sparse Neural Network

Zhongfeng Wang, Wenjian Liu, Jun Lin, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

A Low-latency Sparse-Winograd Accelerator for Convolutional Neural Networks

Zhongfeng Wang, Jun Lin, Tianyi Xu, 2019, ICASSP 2019 - 2019 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

Methodology for Efficient Reconfigurable Architecture of Generative Neural Network

Zhongfeng Wang, Jichen Wang, Wendong Mao, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

An Optimized Architecture For Decomposed Convolutional Neural Networks

Zhongfeng Wang, Jun Lin, Fangxuan Sun, 2018, 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Eadnet: Efficient Architecture for Decomposed Convolutional Neural Networks

Zhongfeng Wang, Jun Lin, Fangxuan Sun, 2018, 2018 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

Efficient fast convolution architectures for convolutional neural network

Xiaohu You, Zhongfeng Wang, Chuan Zhang, 2017, 2017 IEEE 12th International Conference on ASIC (ASICON).

LBFP: Logarithmic Block Floating Point Arithmetic for Deep Neural Networks

Zhongfeng Wang, Jun Lin, Jinming Lu, 2020, 2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

An FPGA-Based Reconfigurable Accelerator for Low-Bit DNN Training

Zhongfeng Wang, Jun Lin, Jinming Lu, 2021, 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

ViTALiTy: Unifying Low-rank and Sparse Approximation for Vision Transformer Acceleration with a Linear Taylor Attention

Chaojian Li, Yingyan Lin, Zhongfeng Wang, 2022, 2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA).

Design Light-weight 3D Convolutional Networks for Video Recognition Temporal Residual, Fully Separable Block, and Fast Algorithm pdf

Zhongfeng Wang, Jun Lin, Haonan Wang, 2019, ArXiv.

A Hidden DCT-Based Invisible Watermarking Method for Low-Cost Hardware Implementations

Zhongfeng Wang, Yuanyong Luo, Yuxuan Wang, 2021, Electronics.

Hardware Accelerator for Multi-Head Attention and Position-Wise Feed-Forward in the Transformer pdf

Siyuan Lu, Meiqi Wang, Jun Lin, 2020, 2020 IEEE 33rd International System-on-Chip Conference (SOCC).

A Universal Approximation Method and Optimized Hardware Architectures for Arithmetic Functions Based on Stochastic Computing

Zhongfeng Wang, Zhonghai Lu, Yuou Qiu, 2020, IEEE Access.

E-LSTM: An Efficient Hardware Architecture for Long Short-Term Memory

Zhongfeng Wang, Meiqi Wang, Jun Lin, 2019, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

DynExit: A Dynamic Early-Exit Strategy for Deep Residual Networks

Zhongfeng Wang, Meiqi Wang, Li Du, 2019, 2019 IEEE International Workshop on Signal Processing Systems (SiPS).

Accelerating Recurrent Neural Networks: A Memory-Efficient Approach

Zhongfeng Wang, Jun Lin, Zhisheng Wang, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

TIE: Energy-efficient Tensor Train-based Inference Engine for Deep Neural Network

Chunhua Deng, Zhongfeng Wang, Xuehai Qian, 2019, 2019 ACM/IEEE 46th Annual International Symposium on Computer Architecture (ISCA).

Efficient Precision-Adjustable Architecture for Softmax Function in Deep Learning

Danyang Zhu, Siyuan Lu, Meiqi Wang, 2020, IEEE Transactions on Circuits and Systems II: Express Briefs.

Transform-Based Feature Map Compression for CNN Inference

Meiqi Wang, Yubo Shi, Zhongfeng Wang, 2021, 2021 IEEE International Symposium on Circuits and Systems (ISCAS).

A High-Speed and Low-Complexity Architecture for Softmax Function in Deep Learning

Danyang Zhu, Zhongfeng Wang, Meiqi Wang, 2018, 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

FACCU: Enable Fast Accumulation for High-Speed DSP Systems

Zhongfeng Wang, Xin Cheng, Meiqi Wang, 2022, IEEE Transactions on Circuits and Systems - II - Express Briefs.

Dynamical Textures Modeling via Joint Video Dictionary Learning

Zhongfeng Wang, Xian Wei, Martin Kleinsteuber, 2017, IEEE Transactions on Image Processing.

An Efficient FPGA Accelerator Optimized for High Throughput Sparse CNN Inference

Zhongfeng Wang, Yufei Ma, Jiayu Wen, 2020, 2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

A Universal Efficient Circular-Shift Network for Reconfigurable Quasi-Cyclic LDPC Decoders

Zhongfeng Wang, Hangxuan Cui, Suwen Song, 2022, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An Efficient Reconfigurable Encoder for the IEEE 1901 Standard

Zhongfeng Wang, Yuxing Chen, Hangxuan Cui, 2022, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An Area-Efficient Message Passing Detector for Massive MIMO Systems

Zhongfeng Wang, Suwen Song, 2022, IEEE Transactions on Circuits and Systems I: Regular Papers.

High-Speed FPGA Implementation of SIKE Based on an Ultra-Low-Latency Modular Multiplier

Zhongfeng Wang, Bo Wu, Jing Tian, 2021, IEEE Transactions on Circuits and Systems I: Regular Papers.

Power optimization for VLSI circuits and systems

Zhongfeng Wang, Guoqiang Hang, Peiyi Zhao, 2010, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.

Low power design of vlsi circuits and systems

Zhongfeng Wang, Peiyi Zhao, P. Zhao, 2009, 2009 IEEE 8th International Conference on ASIC.

Low Power Design ofVLSI Circuits and Systems

Peiyi Zhao, Zhongfeng Wang, P. Zhao, 2009 .

Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes

Zhongfeng Wang, Zhiqiang Cui, Zhongfeng Wang, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Generalized Analog-to-Information Converter With Analysis Sparse Prior

Zhongfeng Wang, Hui Qian, Xinxin Song, 2021, IEEE Transactions on Circuits and Systems I: Regular Papers.

Error correction for multi-level NAND flash memory using Reed-Solomon codes

Zhongfeng Wang, Xinmiao Zhang, Bainan Chen, 2008, 2008 IEEE Workshop on Signal Processing Systems.

Federated Regularization Learning: an Accurate and Safe Method for Federated Learning

Meiqi Wang, Zhongfeng Wang, Tianqi Su, 2021, 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS).

A lightweight face detector by integrating the convolutional neural network with the image pyramid

Jun Lin, Zhongfeng Wang, Jiaying Liu, 2020, Pattern Recognit. Lett..

Learning Robust and Lightweight Model through Separable Structured Transformations pdf

Xian Wei, Xuan Tang, Hai Lan, 2021, ArXiv.

A High-Speed FPGA-Based Hardware Implementation for Leighton-Micali Signature

Zhongfeng Wang, Yifeng Song, Jing Tian, 2023, IEEE Transactions on Circuits and Systems I: Regular Papers.

Compressed Level Crossing Sampling for Ultra-Low Power IoT Devices

Brian M. Sadler, Zhongfeng Wang, Liang Liu, 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

A Uniform Molecular Low-Density Parity Check Decoder.

X. You, Zhongfeng Wang, J. Zhao, 2018, ACS synthetic biology.

A memory efficient belief propagation decoder for polar codes

Zhongfeng Wang, Xiaoyang Zeng, Xing Liu, 2015, China Communications.

Bebert: Efficient And Robust Binary Ensemble Bert

Hong Wang, Zhongfeng Wang, Chao Fang, 2022, ICASSP 2023 - 2023 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

Evaluations on Deep Neural Networks Training Using Posit Number System

Jun Lin, Zhongfeng Wang, Chao Fang, 2020, IEEE Transactions on Computers.

A High-Speed Codec Architecture for Lagrange Coded Computing

Zhongfeng Wang, Jing Tian, Bohang Xiong, 2022, International Symposium on Circuits and Systems.

A High-Speed Architecture for the Reduction in VDF Based on a Class Group

Zhongfeng Wang, Yifeng Song, Jing Tian, 2020, 2020 IEEE 33rd International System-on-Chip Conference (SOCC).

Design of High-Performance and Area-Efficient Decoder for 5G LDPC Codes

Fakhreddine Ghaffari, David Declercq, Jun Lin, 2021, IEEE Transactions on Circuits and Systems I: Regular Papers.

Compressed Power Spectral Density Estimation via Group-Based Total Variation Minimization

Zhongfeng Wang, Jun Zhou, Sebastian Hoyos, 2016, 2016 IEEE International Workshop on Signal Processing Systems (SiPS).

A Low-Complexity Decoder for Turbo Product Codes Based on Extended Hamming Codes

Zhongfeng Wang, Yaqi Wang, Jun Lin, 2018, 2018 IEEE 18th International Conference on Communication Technology (ICCT).

An Improved Gauss-Seidel Algorithm and Its Efficient Architecture for Massive MIMO Systems

Zhongfeng Wang, Jun Lin, Jing Zeng, 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

LDPC decoding with locally informed dynamic scheduling based on the law of large numbers

Zhongfeng Wang, Xingcheng Liu, S. Liang, 2022, IET Commun..

Counter Random Gradient Descent Bit-Flipping Decoder for LDPC Codes

Zhongfeng Wang, Jun Lin, Keyue Deng, 2021, 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Information Storage Bit-Flipping Decoder for LDPC Codes

Zhongfeng Wang, Jun Lin, Hangxuan Cui, 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Fine-Grained Bit-Flipping Decoding for LDPC Codes

Jun Lin, Yuxing Chen, Hangxuan Cui, 2020, IEEE Transactions on Circuits and Systems II: Express Briefs.

An Enhanced Offset Min-Sum decoder for 5G LDPC Codes

David Declercq, Zhongfeng Wang, Khoa LeTrung, 2019, 2019 25th Asia-Pacific Conference on Communications (APCC).

A Decomposition Mapping based Quantized Belief Propagation Decoding for 5G LDPC Codes

David Declercq, Zhongfeng Wang, Ghaffari Fakhreddine, 2019, 2019 19th International Symposium on Communications and Information Technologies (ISCIT).

A Novel Low-Complexity Joint Coding and Decoding Algorithm for NB-LDPC Codes

Zhongfeng Wang, Jun Lin, Jing Tian, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

An Improved Gradient Descent Bit-Flipping Decoder for LDPC Codes

Zhongfeng Wang, Jun Lin, Hangxuan Cui, 2019, IEEE Transactions on Circuits and Systems I: Regular Papers.

An Improved Variable-Node-Based BP Decoding Algorithm for NAND Flash Memory

Zhongfeng Wang, Xingcheng Liu, Guojun Yang, 2018, 2018 IEEE 18th International Conference on Communication Technology (ICCT).

Design of Binary LDPC Codes With Parallel Vector Message Passing

Zhongfeng Wang, Xingcheng Liu, Shuo Liang, 2018, IEEE Transactions on Communications.

An efficient post processing scheme to lower the error floor of LDPC decoders

Zhongfeng Wang, Jun Lin, Wenjie Li, 2017, 2017 IEEE 17th International Conference on Communication Technology (ICCT).

A reduced complexity decoding algorithm for NB-LDPC codes

Zhongfeng Wang, Jun Lin, Suwen Song, 2017, 2017 IEEE 17th International Conference on Communication Technology (ICCT).

Advanced Baseband Processing Algorithms, Circuits, and Implementations for 5G Communication

Zhongfeng Wang, Yuan-Hao Huang, Chuan Zhang, 2017, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Algorithm and architecture for joint detection and decoding for MIMO with LDPC codes

Xiaohu You, Zhongfeng Wang, Chuan Zhang, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

Efficient symbol reliability based decoding for QCNB-LDPC codes

Zhongfeng Wang, Chuan Zhang, Leixin Zhou, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

Memory efficient EMS decoding for non-binary LDPC codes

Zhongfeng Wang, Leixin Zhou, Yun Chen, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

Efficient EMS decoding for non-binary LDPC codes

Zhongfeng Wang, Leixin Zhou, Jin Sha, 2012, 2012 International SoC Design Conference (ISOCC).

Nonbinary LDPC Code Decoder Architecture With Efficient Check Node Processing

Zhongfeng Wang, Kai He, Jin Sha, 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.

Reduced-complexity column-layered decoding and implementation for LDPC codes pdf

Zhongfeng Wang, Xinmiao Zhang, Zhiqiang Cui, 2011, IET Commun..

A High-Throughput LDPC Decoder Architecture With Rate Compatibility

Zhongfeng Wang, Xinming Huang, Kai Zhang, 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

VLSI Design for Low-Density Parity-Check Code Decoding

Jin Sha, Zhiqiang Cui, Zhongfeng Wang, 2011, IEEE Circuits and Systems Magazine.

Low power decoder design for QC-LDPC codes

Zhongfeng Wang, Kai He, Jin Sha, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

Layered decoding for non-binary LDPC codes

Zhongfeng Wang, Shuai Zhou, Jin Sha, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

Iterative symbol-by-symbol decoding of LDPC codes and constellation mapping for multilevel modulation

Zhongfeng Wang, Huaping Liu, Hongtao Jiang, 2010, 2010 5th International ICST Conference on Communications and Networking in China.

A dual-rate LDPC decoder for china multimedia mobile broadcasting systems

Kai Zhang, Zhongfeng Wang, Xinming Huang, 2010, IEEE Transactions on Consumer Electronics.

Efficient Decoder Design for Nonbinary Quasicyclic LDPC Codes

Zhongfeng Wang, Jun Lin, Jin Sha, 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

An improved min-sum based column-layered decoding algorithm for LDPC codes

Zhongfeng Wang, Jun Lin, Jin Sha, 2009, 2009 IEEE Workshop on Signal Processing Systems.

Decoder Design for RS-Based LDPC Codes

Zhongfeng Wang, Jun Lin, Jin Sha, 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

High-throughput layered decoder implementation for quasi-cyclic LDPC codes

Kai Zhang, Zhongfeng Wang, Xinming Huang, 2009, IEEE Journal on Selected Areas in Communications.

An Area-Efficient LDPC Decoder Architecture and Implementation for CMMB Systems

Kai Zhang, Zhongfeng Wang, Xinming Huang, 2009, 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors.

LDPC decoder design for IEEE 802.15 standard

Jun Lin, Zhongfeng Wang, Li Li, 2009, 2009 IEEE International Symposium on Circuits and Systems.

LDPC decoder design for high rate wireless personal area networks

Zhongfeng Wang, Jun Lin, Jin Sha, 2009, IEEE Transactions on Consumer Electronics.

High-Throughput Layered LDPC Decoding Architecture

Zhongfeng Wang, Youjian Liu, Zhiqiang Cui, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Multi-Gb/s LDPC Code Design and Implementation

Zhongfeng Wang, Jin Sha, Li Li, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Efficient decoder design for high-throughput LDPC decoding

Zhongfeng Wang, Xinmiao Zhang, Qingwei Jia, 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

Low-complexity shift-LDPC decoder for high-speed communication systems

Zhongfeng Wang, Chuan Zhang, Jun Lin, 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

Improved low-complexity low-density parity-check decoding

Zhongfeng Wang, Zhiqiang Cui, Zhongfeng Wang, 2008, IET Commun..

Extended layered decoding of LDPC codes

Zhongfeng Wang, Zhiqiang Cui, Zhongfeng Wang, 2008, GLSVLSI '08.

Studies on Practical Low Complexity Decoding of Low-Density Parity-Check Codes

Zhongfeng Wang, Zhiqiang Cui, Zhongfeng Wang, 2007, 2007 IEEE Workshop on Signal Processing Systems.

Efficient Message Passing Architecture for High Throughput LDPC Decoder

Zhongfeng Wang, Zhiqiang Cui, Zhongfeng Wang, 2007, 2007 IEEE International Symposium on Circuits and Systems.

A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes

Zhongfeng Wang, Zhiqiang Cui, Zhongfeng Wang, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An FPGA Implementation of Array LDPC Decoder

Zhongfeng Wang, Jin Sha, Li Li, 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

Efficient Decoder Implementation for QC-LDPC Codes

Jin Sha, Minglun Gao, Zhongfeng Wang, 2006, 2006 International Conference on Communications, Circuits and Systems.

Area-efficient parallel decoder architecture for high rate QC-LDPC codes

Zhongfeng Wang, Zhiqiang Cui, Zhongfeng Wang, 2006, 2006 IEEE International Symposium on Circuits and Systems.

A memory efficient FPGA implementation of quasi-cyclic LDPC decoder

Zhongfeng Wang, Li Li, Jin Sha, 2006 .

Self reliability based weighted bit-flipping decoding for low-density parity-check codes

Zhongfeng Wang, Jin Sha, Li Li, 2006 .

High-throughput and memory efficient LDPC decoder architecture

Zhongfeng Wang, Jin Sha, Li Li, 2006 .

On finite precision implementation of low density parity check codes decoder

Tong Zhang, Keshab K. Parhi, Zhongfeng Wang, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

A Reliability Profile Based Low-Complexity Dynamic Schedule LDPC Decoding

Tianjiao Xie, Ruijia Yuan, Zhongfeng Wang, 2022, IEEE Access.

Improved Decoding Algorithms of LDPC Codes Based on Reliability Metrics of Variable Nodes

Dong Yang, Zhongfeng Wang, Xingcheng Liu, 2019, IEEE Access.

Flexible LDPC Decoder Design for Multigigabit-per-Second Applications

Zhongfeng Wang, Chuan Zhang, Jun Lin, 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

An Efficient VLSI Architecture for Nonbinary LDPC Decoders

Zhongfeng Wang, Jun Lin, Jin Sha, 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

A DNN Optimization Framework with Unlabeled Data for Efficient and Accurate Reconfigurable Hardware Inference

Li Du, Yuan Du, Zhongfeng Wang, 2021, 2021 IEEE International Symposium on Circuits and Systems (ISCAS).

AC-PM: An Area-Efficient and Configurable Polynomial Multiplier for Lattice Based Cryptography

Zhongfeng Wang, Jing Tian, Minghao Li, 2023, IEEE Transactions on Circuits and Systems I: Regular Papers.

Reconfigurable and High-Efficiency Polynomial Multiplication Accelerator for CRYSTALS-Kyber

Zhongfeng Wang, Jing Tian, Minghao Li, 2023, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications

Zhongfeng Wang, Chao Fang, Qiong Li, 2023, 2023 IEEE International Symposium on Circuits and Systems (ISCAS).

Training Deep Neural Networks Using Posit Number System

Siyuan Lu, Zhongfeng Wang, Li Du, 2019, 2019 32nd IEEE International System-on-Chip Conference (SOCC).

DARM: A Low-Complexity and Fast Modular Multiplier for Lattice-Based Cryptography

Zhongfeng Wang, Jing Tian, Xiao Hu, 2021, 2021 IEEE 32nd International Conference on Application-specific Systems, Architectures and Processors (ASAP).

Efficient Software Implementation of the SIKE Protocol Using a New Data Representation

Jun Lin, Zhe Liu, Zhongfeng Wang, 2022, IEEE Transactions on Computers.

Fast Modular Multipliers for Supersingular Isogeny-Based Post-Quantum Cryptography

Jun Lin, Zhongfeng Wang, Jing Tian, 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An Efficient and Flexible Accelerator Design for Sparse Convolutional Neural Networks

Jun Lin, Zhongfeng Wang, Xiaoru Xie, 2021, IEEE Transactions on Circuits and Systems I: Regular Papers.

A Precision-Scalable Energy-Efficient Convolutional Neural Network Accelerator

Jun Lin, Zhongfeng Wang, Wenjian Liu, 2020, IEEE Transactions on Circuits and Systems I: Regular Papers.

Efficient Hardware Architectures for Deep Convolutional Neural Network

Zhongfeng Wang, Jun Lin, Jichen Wang, 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

LSMQ: A Layer-Wise Sensitivity-Based Mixed-Precision Quantization Method for Bit-Flexible CNN Accelerator

Zhongfeng Wang, Kai Chen, Yimin Huang, 2021, 2021 18th International SoC Design Conference (ISOCC).

A Flexible and Efficient FPGA Accelerator for Various Large-Scale and Lightweight CNNs

Zhongfeng Wang, Meiqi Wang, Yufei Ma, 2022, IEEE Transactions on Circuits and Systems I: Regular Papers.

Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base

Yajun Ha, Yuxuan Wang, Siyuan Chen, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Dynamical Textures Modeling via Joint Video Dictionary Learning

Hao Shen, M. Kleinsteuber, Zhongfeng Wang, 2017, IEEE Transactions on Image Processing.

Automatic Model-Based Dataset Generation for High-Level Vision Tasks of Autonomous Driving in Haze Weather

Jiaying Liu, Wenhan Yang, Zhongfeng Wang, 2023, IEEE Transactions on Industrial Informatics.

Area-Efficient Scaling-Free DFT/FFT Design Using Stochastic Computing

Zhongfeng Wang, Yanzhi Wang, Bo Yuan, 2016, IEEE Transactions on Circuits and Systems II: Express Briefs.

Low-Latency Hardware Accelerator for Improved Engle-Granger Cointegration in Pairs Trading

Jun Lin, Siyuan Lu, Shuang Liang, 2021, IEEE Transactions on Circuits and Systems I: Regular Papers.

An Efficient Convolution Core Architecture for Privacy-Preserving Deep Learning

Zhongfeng Wang, Yizhi Wang, Jun Lin, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

Towards an optimal trade-off of Viterbi Decoder Design

Zhongfeng Wang, Li Li, Zhiqiang Cui, 2009, 2009 IEEE International Symposium on Circuits and Systems.

Design of Sequential Elements for Low Power Clocking System

Zhongfeng Wang, Peiyi Zhao, Nan Wang, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Super-FEC Codes for 40/100 Gbps Networking

Zhongfeng Wang, Zhongfeng Wang, 2012, IEEE Communications Letters.

Area-efficient high-speed decoding schemes for turbo decoders

Keshab K. Parhi, Zhongfeng Wang, Zhipei Chi, 2002, IEEE Trans. Very Large Scale Integr. Syst..

VLSI implementation issues of TURBO decoder design for wireless applications

Keshab K. Parhi, Zhongfeng Wang, H. Suzuki, 1999, 1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461).

LSTM-Based Quantitative Trading Using Dynamic K-Top and Kelly Criterion

Jun Lin, Siyuan Lu, Zhongfeng Wang, 2020, 2020 International Joint Conference on Neural Networks (IJCNN).

Prefender: A Prefetching Defender Against Cache Side Channel Attacks as a Pretender

Zhongfeng Wang, Jiayi Huang, Lang Feng, 2022, IEEE Transactions on Computers.

NASA: Neural Architecture Search and Acceleration for Hardware Inspired Hybrid Networks

Haoran You, Yingyan Lin, Zhongfeng Wang, 2022, 2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

An Efficient FPGA Accelerator for Point Cloud

Zhongfeng Wang, Jun Lin, W. Mao, 2022, 2022 IEEE 35th International System-on-Chip Conference (SOCC).

Efficient Reconfigurable Hardware Core for Convolutional Neural Networks

Zhongfeng Wang, Yi Xie, Bo Yuan, 2018, 2018 52nd Asilomar Conference on Signals, Systems, and Computers.

ETA: An Efficient Training Accelerator for DNNs Based on Hardware-Algorithm Co-Optimization

Zhongfeng Wang, Jinming Lu, Chao Ni, 2022, IEEE Transactions on Neural Networks and Learning Systems.