Kenji Takahashi

High-Aspect-Ratio Copper Via Filling Used for Three-Dimensional Chip Stacking

S. Oh, K. Kondo, J. Sun, 2003 .

Circuits using uniform TFTs based on amorphous In‐Ga‐Zn‐O

Hideo Hosono, Masahiro Hirano, Kenji Nomura, 2007 .

Ultra-high-density 3D chip stacking technology

Kazumasa Tanida, Mitsuo Umemoto, Yoshihiro Tomita, 2003, 53rd Electronic Components and Technology Conference, 2003. Proceedings..

Mobility- and temperature-dependent device model for amorphous In–Ga–Zn–O thin-film transistors

T. Kamiya, H. Hosono, A. Sato, 2014 .

Development of less expensive process technologies for three-dimensional chip stacking with through-vias

Kazumasa Tanida, Mitsuo Umemoto, Toshihiro Yonezawa, 2004 .

Au Bump Interconnection in 20 µm Pitch on 3D Chip Stacking Technology

Kazumasa Tanida, Mitsuo Umemoto, Yoshihiro Tomita, 2003 .

3D Chip Stacking Utilizing 20 μm-Pitch Micro Cu Bump Interconnection

Kenji Takahashi, K. Tanida, M. Umemoto, 2005 .

300 mm wafer-level hybrid bonding for Cu/interlayer dielectric bonding in vacuum

K. Kikuchi, Kenji Takahashi, M. Fujino, 2019, Japanese Journal of Applied Physics.

Micro Cu Bump Interconnection on 3D Chip Stacking Technology

Y. Tomita, Kenji Takahashi, K. Tanida, 2004 .

Advanced packaging technologies on 3D stacked LSI utilizing the micro interconnections and the layered microthin encapsulation

Yoshihiro Tomita, Yoshihiko Nemoto, Tadahiro Morifuji, 2001, 2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220).