Takayuki Shibasaki

发表

A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS

Yoshiyasu Doi, Takayuki Shibasaki, Takuji Yamamoto, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

201 New Condition Monitoring Method of Multiple Faults Generated by Rotary Machine Elements under the Other Operating Machineries Located Close Range Based on Multiplex Element Auto Regressive Model with Single-Input

Takayuki Shibasaki, Hiromitsu Ohta, Shintaro Siota, 2012 .

A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process

Yoshiyasu Doi, Takayuki Shibasaki, Takumi Danjo, 2013, IEEE Journal of Solid-State Circuits.

A 60-GHz Injection-Locked Frequency Divider Using Multi-Order LC Oscillator Topology for Wide Locking Range

Yoshiyasu Doi, Takayuki Shibasaki, Takuji Yamamoto, 2011, IEICE Trans. Electron..

Digital Annealer for High-Speed Solving of Combinatorial optimization Problems and Its Applications

Takayuki Shibasaki, Hirotaka Tamura, Satoshi Matsubara, 2020, 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC).

18-GHz Clock Distribution Using a Coupled VCO Array

Takayuki Shibasaki, Hirotaka Tamura, Tadahiro Kuroda, 2007, IEICE Trans. Electron..

A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS

Takayuki Shibasaki, Takumi Danjo, Hiroki Miyaoka, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS

Yoshiyasu Doi, Takayuki Shibasaki, Win Chaivipas, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

Development and Utilization of Rocket Engine Test Database (ReDak) in Japan Aerospace Exploration Agency

Takayuki Shibasaki, Hideaki Nanri, Daizo Sugimori, 2012 .

24 to 34-Gb/s ×4 multi-rate VCSEL-based optical transceiver with referenceless CDR

Takayuki Shibasaki, Yoichi Koyanagi, Hirotaka Tamura, 2016, 2016 Optical Fiber Communications Conference and Exhibition (OFC).

A 2 × 22Gb/s SFI5.2 CDR/deserializer in 65nm CMOS technology

Yoshiyasu Doi, Takayuki Shibasaki, Takuji Yamamoto, 2009, 2009 Symposium on VLSI Circuits.

6.8 A 36Gb/s Adaptive Baud-Rate CDR with CTLE and 1-Tap DFE in 28nm CMOS

Takayuki Shibasaki, Hirotaka Tamura, Wahid Rahman, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS

Takayuki Shibasaki, Takumi Danjo, Hiroki Miyaoka, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

A 56-Gb/s Wireline Transceiver in 20nm CMOS

Yoshiyasu Doi, Takayuki Shibasaki, Yoichi Koyanagi, 2015, 2015 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS).

A 60-GHz 1.65mW 25.9% locking range multi-order LC oscillator based injection locked frequency divider in 65nm CMOS

Yoshiyasu Doi, Takayuki Shibasaki, Takuji Yamamoto, 2010, IEEE Custom Integrated Circuits Conference 2010.

22.7 4×25.78Gb/s retimer ICs for optical links in 0.13μm SiGe BiCMOS

Takayuki Shibasaki, Yoichi Koyanagi, Hirotaka Tamura, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

22.8 A 24-to-35Gb/s x4 VCSEL driver IC with multi-rate referenceless CDR in 0.13um SiGe BiCMOS

Takayuki Shibasaki, Yoichi Koyanagi, Hirotaka Tamura, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

A 3 Watt 39.8–44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS

Yoshiyasu Doi, Takayuki Shibasaki, Takuji Yamamoto, 2010, IEEE Journal of Solid-State Circuits.

6.6 A 22.5-to-32Gb/s 3.2pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28nm CMOS

Takayuki Shibasaki, Hirotaka Tamura, Wahid Rahman, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

25.78-Gb/s VCSEL-based optical transceiver with retimer-embedded driver and receiver ICs

Takayuki Shibasaki, Yoichi Koyanagi, Hirotaka Tamura, 2015, 2015 Optical Fiber Communications Conference and Exhibition (OFC).

A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS

Takayuki Shibasaki, Hirotaka Tamura, Ali Sheikholeslami, 2017, IEEE Journal of Solid-State Circuits.