Sanroku Tsukamoto

发表

A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology

Sanroku Tsukamoto, Hirotaka Tamura, Tadahiro Kuroda, 2010 .

A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process

Yoshiyasu Doi, Takayuki Shibasaki, Takumi Danjo, 2013, IEEE Journal of Solid-State Circuits.

A 6b, 1GS/s, 9.9mW interpolated subranging ADC in 65nm CMOS

Takumi Danjo, Masanori Hoshino, Sanroku Tsukamoto, 2012, Proceedings of Technical Program of 2012 VLSI Design, Automation and Test.

Ising-Model Optimizer with Parallel-Trial Bit-Sieve Engine

Sanroku Tsukamoto, Hirotaka Tamura, Satoshi Matsubara, 2017, CISIS.

Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC

Sanroku Tsukamoto, Hirotaka Tamura, Tadahiro Kuroda, 2010 .

7-bit 0.8–1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique

Takumi Danjo, Sanroku Tsukamoto, Hiroki Ishikuro, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

Dynamic Architecture and Frequency Scaling in 0.8–1.2 GS/s 7 b Subranging ADC

Takumi Danjo, Sanroku Tsukamoto, Hiroki Ishikuro, 2015, IEEE Journal of Solid-State Circuits.

A 0.8V 10b 8OMS/s 6.5mW Pipelined ADC with Regulated Overdrive Voltage Biasing

Sanroku Tsukamoto, Toshihiko Mori, Masato Yoshioka, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

A 9-bit 100 MS/s SAR ADC with Digitally Assisted Background Calibration

Sanroku Tsukamoto, Tadahiro Kuroda, Xiaolei Zhu, 2012, IEICE Trans. Electron..

A 9-bit 100-MS/s 1.46-mW Tri-Level SAR ADC in 65 nm CMOS

Sanroku Tsukamoto, Tadahiro Kuroda, Yanfei Chen, 2010, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Analog to digital converter and encoder to

Sanroku Tsukamoto, Hiroki Murakami, Toshiaki Endo, 1996 .

A 10b 50MS/s 820µW SAR ADC with on-chip digital calibration

Sanroku Tsukamoto, Takeshi Takayama, Masato Yoshioka, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

A dynamic offset control technique for comparator design in scaled CMOS technology

Sanroku Tsukamoto, Hirotaka Tamura, Tadahiro Kuroda, 2008, 2008 IEEE Custom Integrated Circuits Conference.

A CMOS 6-b, 200 MSample/s, 3 V-supply A/D converter for a PRML read channel LSI

Sanroku Tsukamoto, Ian Juso Dedic, Toshiaki Endo, 1996 .

Advances in Analog-to-Digital Converters over the Last Decade

Sanroku Tsukamoto, 2017, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array

Sanroku Tsukamoto, Tadahiro Kuroda, Xiaolei Zhu, 2012, Proceedings of Technical Program of 2012 VLSI Design, Automation and Test.

FA 9.8: A CMOS 6b 400MSamplels ADC with Error Correction

Sanroku Tsukamoto, Toshiaki Endo, William G. Schofield, 1998 .

A 6-bit, 1-GS/s, 9.9-mW, Interpolated Subranging ADC in 65-nm CMOS

Takumi Danjo, Masanori Hoshino, Sanroku Tsukamoto, 2014, IEEE Journal of Solid-State Circuits.

A 7-bit 1-GS/s Flash ADC with Background Calibration

Sanroku Tsukamoto, Akira Matsuzawa, Masaya Miyahara, 2014, IEICE Trans. Electron..

TP 4.5: A CMOS 6b 200MSamplels 3V-Supply AID Converter for a PRML Read Channel LSI

Sanroku Tsukamoto, Ian Juso Dedic, Toshiaki Endo, 1994 .

A 6b 3GS/s flash ADC with background calibration

Sanroku Tsukamoto, Kenji Ito, Kuniyoshi Kamei, 2009, 2009 IEEE Custom Integrated Circuits Conference.

Split capacitor DAC mismatch calibration in successive approximation ADC

Sanroku Tsukamoto, Hirotaka Tamura, Tadahiro Kuroda, 2009, 2009 IEEE Custom Integrated Circuits Conference.

A 9b 100MS/s 1.46mW SAR ADC in 65nm CMOS

Sanroku Tsukamoto, Tadahiro Kuroda, Yanfei Chen, 2009, 2009 IEEE Asian Solid-State Circuits Conference.

A 10-b 50-MS/s 820- $\mu $W SAR ADC With On-Chip Digital Calibration

Sanroku Tsukamoto, Takeshi Takayama, Masato Yoshioka, 2010, IEEE Transactions on Biomedical Circuits and Systems.

Study of Flash Analog-to-Digital Converters with Background Calibration

Sanroku Tsukamoto, 塚本三六, 2015 .

A 1 GHz CMOS comparator with dynamic offset control technique

Sanroku Tsukamoto, Tadahiro Kuroda, Xiaolei Zhu, 2009, 2009 Asia and South Pacific Design Automation Conference.