P. M. Sobha

发表

Out of order floating point coprocessor for RISC V ISA

Aneesh Raveendran, Vinayak Patil, P. M. Sobha, 2015, 2015 19th International Symposium on VLSI Design and Test.

RISC-V out-of-order data conversion co-processor

Aneesh Raveendran, Vivian Desalphine, Vinayak Patil, 2015, 2015 19th International Symposium on VLSI Design and Test.

Design, implementation and performance of fault-tolerant message passing interface (MPI)

P. M. Sobha, A. David Selvakumar, R. Pitchiah, 2004, Proceedings. Seventh International Conference on High Performance Computing and Grid in Asia Pacific Region, 2004..

HMFPCC: - Hybrid-mode floating point conversion co-processor

Vinayak Patil, P. M. Sobha, A. David Selvakumar, 2015, 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA).

Reconfigurable side channel attack resistant true random number generator

David Selvakumar, P. M. Sobha, Vijay Bahadur, 2016, 2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA).

Area and frequency optimized 1024 point Radix-2 FFT processor on FPGA

P. M. Sobha, Vinay Kumar M, David Selvakumar A, 2015, 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA).