A. David Selvakumar

Out of order floating point coprocessor for RISC V ISA

Aneesh Raveendran, Vinayak Patil, P. M. Sobha, 2015, 2015 19th International Symposium on VLSI Design and Test.

Implementation of NB PHY transceiver of IEEE 802.15.6 WBAN on FPGA

Vivian Desalphine, A. David Selvakumar, Priya Mathew, 2015, 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA).

SCADA with fault tolerant CORBA on fault tolerant LANE ATM

Chester Rebeiro, A. David Selvakumar, R. Pitchiah, 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

RISC-V Half Precision Floating Point Instruction Set Extensions and Co-processor

Aneesh Raveendran, A. David Selvakumar, D. Vivian, 2019, VDAT.

RISC-V out-of-order data conversion co-processor

Aneesh Raveendran, Vivian Desalphine, Vinayak Patil, 2015, 2015 19th International Symposium on VLSI Design and Test.

Design, implementation and performance of fault-tolerant message passing interface (MPI)

P. M. Sobha, A. David Selvakumar, R. Pitchiah, 2004, Proceedings. Seventh International Conference on High Performance Computing and Grid in Asia Pacific Region, 2004..

Bitslice Implementation of AES

Chester Rebeiro, A. David Selvakumar, A. S. L. Devi, 2006, CANS.

HMFPCC: - Hybrid-mode floating point conversion co-processor

Vinayak Patil, P. M. Sobha, A. David Selvakumar, 2015, 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA).

P-FMA: A Novel Parameterized Posit Fused Multiply-Accumulate Arithmetic Processor

Aneesh Raveendran, A. David Selvakumar, Vivian Desalphine, 2021, 2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID).