C. Hashimoto

Threshold-voltage instability of n-channel MOSFET's under bias-temperature aging

N. Shiono, C. Hashimoto, 1982, IEEE Transactions on Electron Devices.

Kinetics of Changes in N f and D it at the Si ‐ SiO2 Interface under Long‐Term Positive as well as Negative Bias‐Temperature Aging

O. Nakajima, N. Shiono, C. Hashimoto, 1983 .

Leakage-current reduction in thin Ta/sub 2/O/sub 5/ films for high-density VLSI memories

H. Oikawa, C. Hashimoto, N. Honma, 1989 .

Reduction of Electron‐Beam‐Induced Damage in MOS Devices Using Three‐Layer Resist with Heavy Metal Interlayer

O. Nakajima, M. Shimaya, C. Hashimoto, 1984 .

A low-temperature MOS LSI process

C. Hashimoto, H. Ushizaka, 1988, IEEE Electron Device Letters.

Electron Beam Induced Damage in Poly‐Si Gate MOS Structures and Its Effect on Long‐Term Stability

O. Nakajima, M. Shimaya, N. Shiono, 1983 .

Defects in a Gate Oxide Grown after the LOCOS Process

Osaake Nakajima, Chisato Hashimoto, Susumu Muramoto, 1979 .