J. Sung

发表

Cycling of defects between trapped negative charge and interface states at the Si‐SiO2 interface

S. Lyon, J. Sung, 1987 .

BEST2-a high performance super self-aligned 3 V/5 V BiCMOS technology with extremely low parasitics for low-power mixed-signal applications

B. Razavi, R. Swartz, J. Sung, 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

Relationship Between Hole Trapping and Interface

S. Lyon, J. Sung, S. Wang, 1988 .

Relationship between hole trapping and interface state generation in metal‐oxide‐silicon structures

Stephen Aplin Lyon, S. Lyon, J. Sung, 1988 .

Reverse short-channel effects on threshold voltage in submicrometer salicide devices

C. Lu, J. Sung, C.-Y. Lu, 1989, IEEE Electron Device Letters.

A half-micron super self-aligned BiCMOS technology for high speed applications

R. G. Swartz, V. D. Archer, G. M. Chin, 1992, 1992 International Technical Digest on Electron Devices Meeting.

Fluorine effect on boron diffusion of p/sup +/ gate devices (MOSFETs)

W. S. Lindenberger, S. J. Wang, C. Lu, 1989, International Technical Digest on Electron Devices Meeting.

Negative charge induced degradation of PMOSFETs with BF/sub 2/-implanted p/sup +/-poly gate

J. Sung, C. Y. Lu, 1989 .

The impact of poly-removal techniques on thin thermal oxide property in poly-buffer LOCOS technology

C. Lu, K. Lee, J. Sung, 1991 .

Practical manufacturing technique for reducing charge-induced gate oxide degradation during ion implantation

James Sung, Kenneth Gordon Moerschel, W. A. Possanza, 1999, Advanced Lithography.

Anomalous C-V characteristics of implanted poly MOS structure in n/sup +//p/sup +/ dual-gate CMOS technology

C. Lu, S. Hillenius, J. Sung, 1989, IEEE Electron Device Letters.