J. van Aelst

3D stacked IC demonstration using a through Silicon Via First approach

A. Jourdain, E. Beyne, B. Parvais, 2008, 2008 IEEE International Electron Devices Meeting.

3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias

E. Beyne, B. Swinnen, L. Bogaerts, 2006, 2006 International Electron Devices Meeting.

Role of dielectric and barrier integrity in reliability of sub-100 nm copper low-k interconnects

G. Beyer, K. Maex, Y. Travaly, 2005, 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual..

Integration of Single Damascene 85/85 nm L/S copper trenches in Black Diamond using 193 nm optical lithography with dipole illumination

M. Van Hove, S. Demuynck, K. Maex, 2003, Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695).