G. Chindalore

Experimental determination of threshold voltage shifts due to quantum mechanical effects in MOS electron and hole inversion layers

A. Tasch, C. Maziar, S. Jallepalli, 1997, IEEE Electron Device Letters.

A new combination-erase technique for erasing nitride based (SONOS) nonvolatile memories

C.T. Swift, D. Burnett, G.L. Chindalore, 2003, IEEE Electron Device Letters.

Experimental determination of electron and hole mobilities in MOS accumulation layers

A. Tasch, J. B. Mckeon, C. Maziar, 1997, IEEE Electron Device Letters.

An embedded 90 nm SONOS nonvolatile memory utilizing hot electron programming and uniform tunnel erase

C.T. Swift, A. Hoefler, G.L. Chindalore, 2002, Digest. International Electron Devices Meeting,.

Characterization and optimization of the SiO2/SiC metal-oxide semiconductor interface

Michael R. Melloch, John W. Palmour, M. Melloch, 1995 .

Models for electron and hole mobilities in MOS accumulation layers

A. Tasch, S. Banerjee, C. Maziar, 1999 .

Embedded split-gate flash memory with silicon nanocrystals for 90nm and beyond

Ko-Min Chang, H. Gasquet, Sung-Taeg Kang, 2008, 2008 Symposium on VLSI Technology.

Temperature characterization and modeling of electron and hole mobilities in MOS accumulation layers

A. Tasch, C. Maziar, S. Mudanai, 1998, 56th Annual Device Research Conference Digest (Cat. No.98TH8373).