S. Smith

Experimental determination of threshold voltage shifts due to quantum mechanical effects in MOS electron and hole inversion layers

A. Tasch, C. Maziar, S. Jallepalli, 1997, IEEE Electron Device Letters.

Barrier integrity testing of Ta using triangular voltage sweep and a novel CV-BTS test structure

S. Smith, K. Pfeifer, G. Book, 2002 .

High-performance 40nm gate length InSb p-channel compressively strained quantum well field effect transistors for low-power (VCC=0.5V) logic applications

G. Dewey, R. Pillarisetty, M. Radosavljevic, 2008, 2008 IEEE International Electron Devices Meeting.