T. Trajkovic

Retrograde p-Well for 10-kV Class SiC IGBTs

F. Udrea, M. Antoniou, Amit K. Tiwari, 2019, IEEE Transactions on Electron Devices.

Transient Performance of >10kV SiC IGBT with an Optimized Retrograde p-Well

F. Udrea, M. Antoniou, P. Gammon, 2019 .

Single event effects and total ionising dose in 600V Si-on-SiC LDMOS transistors for rad-hard space applications

Denis Flandre, V. Pathirana, C. W. Chan, 2017, 2017 47th European Solid-State Device Research Conference (ESSDERC).

Design and Fabrication of Silicon-on-Silicon-Carbide Substrates and Power Devices for Space Applications

D. Flandre, J. Gardner, P. Mawby, 2017 .

Performance Improvement of >10kV SiC IGBTs with Retrograde p-Well

F. Udrea, M. Antoniou, Amit K. Tiwari, 2019, Materials Science Forum.

On the robustness of ultra-high voltage 4H-SiC IGBTs with an optimized retrograde p-well

F. Udrea, M. Antoniou, Amit K. Tiwari, 2019, 2019 IEEE 12th International Symposium on Diagnostics for Electrical Machines, Power Electronics and Drives (SDEMPED).

Development, characterisation and simulation of wafer bonded Si-on-SiC substrates

D. Flandre, V. Kilchytska, V. Pathirana, 2017 .

Novel Buried Field Rings Edge Termination for 4H-SiC High-Voltage Devices

P. Godignon, A. Mihaila, F. Udrea, 2003 .

Buried field rings - a novel edge termination method for 4H-SiC high voltage devices

P. Godignon, A. Mihaila, F. Udrea, 2002, Proceedings. International Semiconductor Conference.

Design and fabrication of a power Si/SiC LDMOSFET for high temperature applications

C. W. Chan, D. Flandre, J. Gardner, 2017 .

Optimization of Power VDMOSFET's Process Parameters by Neural Networks

Srdjan Milenkovic, Dragan Pantic, Tatjana Trajkovic, 1995, ESSDERC '95: Proceedings of the 25th European Solid State Device Research Conference.

Inverse modeling of semiconductor manufacturing processes by neural networks

V. Litovski, N. Stojadinovic, D. Pantic, 1995, Proceedings of International Conference on Microelectronics.