Y. Shao

发表

Toward Cache-Friendly Hardware Accelerators

Gu-Yeon Wei, D. Brooks, V. Srinivasan, 2015 .

Stitch-X: An Accelerator Architecture for Exploiting Unstructured Sparsity in Deep Neural Networks

A. Parashar, S. Keckler, Zhengya Zhang, 2018 .

Gemmini: An Agile Systolic Array Generator Enabling Systematic Evaluations of Deep-Learning Architectures pdf

Ion Stoica, Krste Asanovic, Hasan Genc, 2019, ArXiv.

GitHub Version 0.0.1

Nesreen K. Ahmed, Krste Asanovic, Ameer Haj-Ali, 2020 .

CoSA: Scheduling by Constrained Optimization for Spatial Accelerators

James Demmel, John Wawrzynek, Aravind Kalaiah, 2021, 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA).

Simba

C. T. Gray, W. Dally, Rangharajan Venkatesan, 2019, Communications of the ACM.

Accelerating General-Purpose Linear Algebra on DNN Accelerators

K. Asanović, B. Nikolić, Jerry Zhao, 2022 .

Full Stack Optimization of Transformer Inference: a Survey

Michael W. Mahoney, K. Keutzer, A. Gholami, 2023, ArXiv.

Hardware Acceleration

Martha A. Kim, Yakun Sophia Shao, Y. Shao, 2018, IEEE Micro.

A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm

William J. Dally, Brucek Khailany, Stephen G. Tell, 2019, 2019 Symposium on VLSI Circuits.

Gemmini: An Agile Systolic Array Generator Enabling Systematic Evaluations of Deep-Learning Architectures

Albert J. Ou, I. Stoica, K. Asanović, 2019, ArXiv.

A 0.32–128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm

William J. Dally, Yanqing Zhang, Brucek Khailany, 2020, IEEE Journal of Solid-State Circuits.

Timeloop: A Systematic Approach to DNN Accelerator Evaluation

Brucek Khailany, Stephen W. Keckler, Joel S. Emer, 2019, 2019 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

INVITED: A Modular Digital VLSI Flow for High-Productivity SoC Design

Christopher Torng, Shreesha Srinath, Brucek Khailany, 2018, 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC).

Co-designing accelerators and SoC interfaces using gem5-Aladdin

Gu-Yeon Wei, David M. Brooks, Vijayalakshmi Srinivasan, 2016, 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

Design and Modeling of Specialized Architectures

Yakun Shao, Y. Shao, 2016 .

Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures

Gu-Yeon Wei, David M. Brooks, Brandon Reagen, 2014, 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA).

Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture

William J. Dally, Yanqing Zhang, Brucek Khailany, 2019, MICRO.

Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration

Jerry Zhao, Ion Stoica, Borivoje Nikolic, 2019, 2021 58th ACM/IEEE Design Automation Conference (DAC).

Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs

Krste Asanovic, Daniel Grubb, Colin Schmidt, 2020, IEEE Micro.

Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration

Jason Clemons, Stephen W. Keckler, Joel S. Emer, 2019, ASPLOS.

Simba

C. T. Gray, W. Dally, Rangharajan Venkatesan, 2021, Commun. ACM.

SNAP: A 1.67 — 21.55TOPS/W Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference in 16nm CMOS

Chester Liu, Stephen W. Keckler, Zhengya Zhang, 2019, 2019 Symposium on VLSI Circuits.

MachSuite: Benchmarks for accelerator design and customized architectures

Gu-Yeon Wei, David M. Brooks, Robert Adolf, 2014, 2014 IEEE International Symposium on Workload Characterization (IISWC).

Energy characterization and instruction-level energy model of Intel's Xeon Phi processor

David M. Brooks, Yakun Sophia Shao, D. Brooks, 2013, International Symposium on Low Power Electronics and Design (ISLPED).

MAGNet: A Modular Accelerator Generator for Neural Networks

William J. Dally, Brucek Khailany, Jason Clemons, 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

SNAP: An Efficient Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference

Stephen W. Keckler, Zhengya Zhang, Yakun Sophia Shao, 2021, IEEE Journal of Solid-State Circuits.

Full Stack Optimization of Transformer Inference

Michael W. Mahoney, K. Keutzer, A. Gholami, 2023 .

ISA-independent workload characterization and its implications for specialized architectures

David M. Brooks, Yakun Sophia Shao, D. Brooks, 2013, 2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

Efficient emotion recognition using hyperdimensional computing with combinatorial channel encoding and cellular automata pdf

Jan M. Rabaey, Yakun Sophia Shao, Daniel Sun, 2021, Brain Informatics.

Research Infrastructures for Hardware Accelerators

David M. Brooks, Yakun Sophia Shao, D. Brooks, 2015, Research Infrastructures for Hardware Accelerators.

A 16mm2 106.1 GOPS/W Heterogeneous RISC-V Multi-Core Multi-Accelerator SoC in Low-Power 22nm FinFET

Jerry Zhao, Elad Alon, Borivoje Nikolic, 2021, ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC).

Learning A Continuous and Reconstructible Latent Space for Hardware Accelerator Design

J. Wawrzynek, Mahesh Subedar, Y. Shao, 2022, 2022 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

RoSÉ: A Hardware-Software Co-Simulation Infrastructure Enabling Pre-Silicon Full-Stack Robotics SoC Evaluation

B. Nikolić, Y. Shao, Seah Kim, 2023, ISCA.

MoCA: Memory-Centric, Adaptive Execution for Multi-Tenant Deep Neural Networks

K. Asanović, B. Nikolić, Y. Shao, 2023, 2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA).

The Aladdin Approach to Accelerator Design and Modeling

Gu-Yeon Wei, David M. Brooks, Brandon Reagen, 2015, IEEE Micro.

Assisting High-Level Synthesis Improve SpMV Benchmark Through Dynamic Dependence Analysis

Gu-Yeon Wei, Brandon Reagen, David Brooks, 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology

William J. Dally, Yanqing Zhang, Brucek Khailany, 2019, 2019 IEEE Hot Chips 31 Symposium (HCS).

Commercial Products

D. Patterson, Y. Shao, 2020, IEEE Micro.

Vertically Integrated Computing Labs Using Open-Source Hardware Generators and Cloud-Hosted FPGAs

Borivoje Nikolic, Krste Asanovic, Yakun Sophia Shao, 2021, 2021 IEEE International Symposium on Circuits and Systems (ISCAS).

AuRORA: Virtualized Accelerator Orchestration for Multi-Tenant Workloads

K. Asanović, Y. Shao, Seah Kim, 2023, 2023 56th IEEE/ACM International Symposium on Microarchitecture (MICRO).

Stitch-X: An Accelerator Architecture for Exploiting Unstructured Sparsity in Deep Neural Networks

A. Parashar, S. Keckler, Y. Shao, 2018 .

KVQuant: Towards 10 Million Context Length LLM Inference with KV Cache Quantization

A. Gholami, Y. Shao, Sehoon Kim, 2024, ArXiv.

RETROSPECTIVE: Aladdin: a Pre-RTL, Power-Performance Accelerator Simulator Enabling Large Design Space Exploration of Customized Architectures

Brandon Reagen, Gu-Yeon Wei, D. Brooks, 2023 .