T. Garbolino

Low Hardware Overhead Deterministic Logic BIST with Zero-Aliasing

A. Hlawiczka, T. Garbolino, K. Gucwa, 2001 .

A New, Fast Pseudo-Random Pattern Generator for Advanced Logic Built-In Self-Test Structures

T. Garbolino, 2021, Applied Sciences.

A NEW APPROACH TO OPTIMIZATION OF TEST PATTERN GENERATOR STRUCTURE

G. Papa, T. Garbolino, 2010 .

Genetic algorithm for test pattern generator design

Gregor Papa, Tomasz Garbolino, G. Papa, 2010, Applied Intelligence.

Effective BIST for crosstalk faults in interconnects

Krzysztof Gucwa, Tomasz Garbolino, Andrzej Hlawiczka, 2009, 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

A Method to Support Diagnostics of Dynamic Faults in Networks of Interconnections

Tomasz Garbolino, T. Garbolino, 2018 .

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), Kraków, Poland, April 11-13, 2007

Elena Gramatova, Andrzej Krasniewski, Adam Pawlak, 2007, IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems.

Analysis of operation of ring LFSR used for testing of unidirectional interleaved interconnections

Krzysztof Gucwa, Tomasz Garbolino, Andrzej Hlawiczka, 2011, Proceedings of the 18th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2011.