B. Alizadeh

发表

Check High Level Properties in Arithmetic Circuits

B. Alizadeh, Hamid Shojaee, 2003 .

Symbolic model-based diagnosis with auto-correction framework for arithmetic circuits

B. Alizadeh, 2011, 2011 3rd Asia Symposium on Quality Electronic Design (ASQED).

Binary Taylor Diagrams ( BTD ) : An Efficient Way of Implementing Taylor Expansion Diagrams

Z. Navabi, B. Alizadeh, A. Hooshmand, 2022 .

A New High Level Model Based on Integer Equations to Check CTL Properties in VHDL Environment

Z. Navabi, B. Alizadeh, M. R. Kakoee, 2003 .

A Comparative Study of Machine Learning Classifiers for Secure RF-PUF-Based Authentication in Internet of Things

B. Alizadeh, Amir Ashtari, A. Shabani, 2022, Microprocessors and Microsystems.

FPGA-Based Implementation of a Real-Time Object Recognition System Using Convolutional Neural Network

Bijan Alizadeh, Ali Azarmi Gilan, Mohammad Emad, 2020, IEEE Transactions on Circuits and Systems II: Express Briefs.

High-Level Synthesis of Non-Rectangular Multi-Dimensional Nested Loops Using Reshaping and Vectorization

Sahand Salamat, Bijan Alizadeh, Mohammad Reza Azarbad, 2018, 2018 IEEE International Conference on Rebooting Computing (ICRC).

A Resource-Limited Hardware Accelerator for Convolutional Neural Networks in Embedded Vision Applications

Reza Ebrahimpour, Shayan Moini, Bijan Alizadeh, 2017, IEEE Transactions on Circuits and Systems II: Express Briefs.

FPGA-Based Implementation of a Novel Method for Estimating the Brillouin Frequency Shift in BOTDA and BOTDR Sensors

Bijan Alizadeh, Mojtaba Abbasnejad, B. Alizadeh, 2018, IEEE Sensors Journal.

Using integer equations to check PSL properties in RT level design

Zainalabedin Navabi, Bijan Alizadeh, Z. Navabi, 2004, 4th IEEE International Workshop on System-on-Chip for Real-Time Applications.

Word level functional coverage computation

Bijan Alizadeh, B. Alizadeh, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Word-level symbolic simulation in processor verification

Zainalabedin Navabi, Bijan Alizadeh, Z. Navabi, 2004 .

Property checking based on hierarchical integer

Zainalabedin Navabi, Bijan Alizadeh, Z. Navabi, 2004, Proceedings. Fourth International Conference on Application of Concurrency to System Design, 2004. ACSD 2004..

Using integer equations for high level formal verification property checking

Mohammad Reza Kakoee, Bijan Alizadeh, B. Alizadeh, 2003, Fourth International Symposium on Quality Electronic Design, 2003. Proceedings..

CTL Property Checking Based on a New High Level Model Without Equation Solving

Z. Navabi, B. Alizadeh, 2003 .

A Scalable Formal Debugging Approach with Auto-Correction Capability Based on Static Slicing and Dynamic Ranking for RTL Datapath Designs

Payman Behnam, Bijan Alizadeh, Somayeh Sadeghi Kohan, 2015, IEEE Transactions on Computers.

Improving polynomial datapath debugging with HEDs

Masahiro Fujita, Zainalabedin Navabi, Payman Behnam, 2014, 2014 19th IEEE European Test Symposium (ETS).

Systematic Design Space Exploration of Floating-Point Expressions on FPGA

Bijan Alizadeh, Alireza Mahzoon, B. Alizadeh, 2017, IEEE Transactions on Circuits and Systems II: Express Briefs.

OptiFEX: A Framework for Exploring Area-Efficient Floating Point Expressions on FPGAs With Optimized Exponent/Mantissa Widths

Bijan Alizadeh, Alireza Mahzoon, B. Alizadeh, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Multi-objective Optimization of Floating Point Arithmetic Expressions Using Iterative Factorization

Bijan Alizadeh, Alireza Mahzoon, B. Alizadeh, 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.

Groebner basis based formal verification of large arithmetic circuits using Gaussian elimination and cone-based polynomial extraction

Farimah Farahmandi, Bijan Alizadeh, B. Alizadeh, 2015, Microprocess. Microsystems.

PODEM: A low-cost property-based design modification for detecting Hardware Trojans in resource-constraint IoT devices

Ahmad Shabani, Bijan Alizadeh, B. Alizadeh, 2020, J. Netw. Comput. Appl..

Automated Formal Equivalence Verification of Pipelined Nested Loops in Datapath Designs pdf

Payman Behnam, Sajjad Taheri, Bijan Alizadeh, 2017, ArXiv.

Formal equivalence verification and debugging techniques with auto-correction mechanism for RTL designs

Payman Behnam, Bijan Alizadeh, B. Alizadeh, 2013, Microprocess. Microsystems.

A formal approach to debug polynomial datapath designs

Bijan Alizadeh, B. Alizadeh, 2012, 17th Asia and South Pacific Design Automation Conference.

Modular equivalence verification of polynomial datapaths with multiple word-length operands

Masahiro Fujita, Bijan Alizadeh, M. Fujita, 2011, 2011 IEEE International High Level Design Validation and Test Workshop.

Analytical performance model for FPGA-based reconfigurable computing

Bijan Alizadeh, Hossein Mehri, B. Alizadeh, 2015, Microprocess. Microsystems.

Modular arithmetic decision procedure with auto-correction mechanism

Masahiro Fujita, Bijan Alizadeh, M. Fujita, 2009, 2009 IEEE International High Level Design Validation and Test Workshop.

Genetic-Algorithm-Based FPGA Architectural Exploration Using Analytical Models

Bijan Alizadeh, Hossein Mehri, B. Alizadeh, 2016, ACM Trans. Design Autom. Electr. Syst..

An analytical dynamic and leakage power model for FPGAs

Bijan Alizadeh, Hossein Mehri, B. Alizadeh, 2014, 2014 22nd Iranian Conference on Electrical Engineering (ICEE).

SAT-Based Integrated Hardware Trojan Detection and Localization Approach Through Path-Delay Analysis

Bijan Alizadeh, Mohammad Sabri, Ahmad Shabani, 2021, IEEE Transactions on Circuits and Systems II: Express Briefs.