M. Morisue

A new Josephson /spl delta/-gate ternary-valued logic

A. Haidar, Z. Othman, M. Morisue, 2002, The 14th International Conference on Microelectronics,.

A novel ternary logic circuit using Josephson junction

M. Morisue, K. Oochi, M. Nishizawa, 1989 .

A superconducting ternary systolic array processor

Mititada Morisue, Fu-Qiang Li, M. Morisue, 1992, [1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic.

JCTL: a Josephson complementary ternary logic circuit

M. Morisue, M. Nishizawa, K. Ochi, 1988, [1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic.

Backpropagation Algorithm for LOGic Oriented Neural Networks with Quantized Weights and Multilevel Threshold Neurons

Mititada Morisue, Hisato Fujisaka, Takeshi Kamio, 2001 .

Fast Inverters over Finite Field Based on Euclid's Algorithm

Kiyomichi Araki, Mititada Morisue, K. Araki, 1989 .

Analysis of pulse propagation on high-T/sub c/ superconducting transmission lines

A. Kanasugi, M. Morisue, S. Furusawa, 1991 .

Simulation of Computing Circuits with Neural Networks

Mititada Morisue, Taketoshi Mishima, Hisashi Hayashi, 1993 .

A fuzzy processor using Josephson junctions

A. Kanasugi, M. Morisue, N. Ishii, 1991 .

A Genetic Approach to Placement Using a New Coding Technique

Hiroyuki Shindo, Mititada Morisue, Akinori Kanasugi, 1996 .

A content addressable memory using Josephson junctions

M. Morisue, M. Morisue, M. Kaneko, 1991, IEEE Transactions on Applied Superconductivity.

A high-speed adder using Gunn diodes

S. Kataoka, K. Komamiya, M. Morisue, 1971 .

Binary and multi-valued cellular array models of linear distributed parameter systems

Mititada Morisue, Hisato Fujisaka, Daisuke Hamano, 2003, 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003.