K. Shoji

Universal-Vdd 0.65-2.0V 32 kB cache using voltage-adapted timing-generation scheme and a lithographical-symmetric cell

K. Ishibashi, S. Ikeda, K. Osada, 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

Fabrication and properties of one-mask-patterned ferroelectric integrated capacitors

M. Moniwa, T. Kaga, K. Torii, 1997 .

Formation of SiGe/Si Heterostructures by Low-Temperature Germanium Ion Implantation

T. Nagano, Cary Y. Yang, K. Shoji, 1992 .

Characterization of germanium implanted Si1−xGex layer

T. Nagano, Cary Y. Yang, K. Shoji, 1993 .

Characterization of SiGe/Si heterostructures formed by Ge+ and C+ implantation

T. Nagano, Cary Y. Yang, K. Shoji, 1990 .

Universal-Vdd 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell

Kenichi Osada, Kenichi Kuroda, Masood Khan, 2001, IEEE J. Solid State Circuits.

An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture

Takeshi Sakata, Eiji Takeda, Mayu Aoki, 1995, IEEE J. Solid State Circuits.

An experimental 220 MHz 1 Gb DRAM

Masashi Horiguchi, Takeshi Sakata, Fumio Murai, 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

Improved crystalline quality of Si1−xGex formed by low‐temperature germanium ion implantation

T. Nagano, Cary Y. Yang, K. Shoji, 1992 .