F. Allibert

发表

M. Mojarradi, B. Blalock, S. Cristoloveanu, 2002, 32nd European Solid-State Device Research Conference.

Physical Models of Planar Spiral Inductor Integrated on the High-Resistivity and Trap-Rich Silicon-on-Insulator Substrates

Xinen Zhu, I. Radu, Yumin Lu, 2017, IEEE Transactions on Electron Devices.

Characterization and role of deep traps on the radio frequency performances of high resistivity substrates

J. Raskin, M. Cassé, M. Rack, 2021 .

RF and linear performance of commercial 200 mm trap-rich HR-SOI wafers for SoC applications

F. Allibert, E. Desbonnets, I. Bertrand, 2013, 2013 IEEE 13th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems.

Evaluation of sSOI wafers for 22nm node and beyond

W. Schwarzenbach, B. Nguyen, M. Vinet, 2012, 2012 IEEE International SOI Conference (SOI).

High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond

M. Khare, S. Luning, O. Faynot, 2013, 2013 IEEE International Electron Devices Meeting.

Defect delineation and characterization in SiGe, Ge and other semiconductor-on-insulator structures

F. Allibert, A. Abbadie, F. Brunier, 2009 .

Impact of free surface passivation on silicon on insulator buried interface properties by pseudotransistor characterization

Frederic Allibert, Sorin Cristoloveanu, Harold J. Hovel, 2007 .

In Situ Characterization of Bias Instability in Bare SOI Wafers by Pseudo-MOSFET Technique

S. Cristoloveanu, F. Gámiz, A. Ohata, 2014, IEEE Transactions on Device and Materials Reliability.

Direct point-contact characterization of Bias instability on bare SOI wafers

S. Cristoloveanu, F. Gámiz, A. Ohata, 2013, 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

A new characterization technique for SOI wafers: Split C(V) in pseudo-MOSFET configuration

G. Ghibaudo, C. Mazure, S. Cristoloveanu, 2013 .

Impact of effective capacitance area on the characterization of SOI Wafers by Split-C(V) in Pseudo-MOSFET configuration

S. Cristoloveanu, F. Gámiz, A. Ohata, 2012, 2012 International Semiconductor Conference Dresden-Grenoble (ISCDG).

Static and low-frequency noise characterization of ultrathin SOI with very thin BOX in pseudo-MOSFET configuration

G. Ghibaudo, F. Allibert, I. Ionica, 2011, 2011 International Semiconductor Device Research Symposium (ISDRS).

Low-frequency noise in SOI pseudo-MOSFET with pressure probes

G. Ghibaudo, S. Cristoloveanu, F. Allibert, 2011 .

Three-interface pseudo-MOSFET models for the characterization of SOI wafers with ultrathin film and BOX

S. Cristoloveanu, F. Gámiz, N. Rodriguez, 2011 .

Advances in the pseudo-MOSFET characterization method

S. Cristoloveanu, A. Ohata, X. Mescot, 2010, CAS 2010 Proceedings (International Semiconductor Conference).

Impact of surface and buried interface passivation on ultrathin SOI electrical properties

S. Cristoloveanu, F. Allibert, G. Hamaide, 2008, 2008 IEEE International SOI Conference.

Systematic evaluation of SOI Buried Oxide reliability for partially depleted and fully depleted applications

W. Schwarzenbach, B. Nguyen, F. Allibert, 2015, 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

RF Small- and Large-Signal Characteristics of CPW and TFMS Lines on Trap-Rich HR-SOI Substrates

Frederic Allibert, Jean-Pierre Raskin, Martin Rack, 2018, IEEE Transactions on Electron Devices.

RF performance of passive components on state-of-art trap rich silicon-on-insulator substrates

Xinen Zhu, I. Radu, Yumin Lu, 2016, 2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Internal Dissolution of Buried Oxide in SOI Wafers

F. Allibert, O. Kononchuk, F. Boedt, 2007 .

Germanium-on-insulator (GeOI) substrates—A novel engineered substrate for future high performance devices

Frederic Allibert, Yves Campidelli, N. Kernevez, 2006 .

On the effective mobility extraction by point-contact techniques on silicon-on-insulator substrates

A. Ohata, N. Rodriguez, C. Márquez, 2015 .

Steep Switching Si Nanowire p-FETs With Dopant Segregated Silicide Source/Drain at Cryogenic Temperature

J. Knoch, D. Grützmacher, Qing-Tai Zhao, 2022, IEEE Electron Device Letters.

Ultra-thin body & buried oxide SOI substrate development and qualification for Fully Depleted SOI device with back bias capability

Frederic Allibert, Bich-Yen Nguyen, Christophe Maleville, 2016 .

Down to 15nm BOX: SOI extendability for planar fully depleted application beyond 22FD

L. Grenouillet, W. Schwarzenbach, C. Le Royer, 2016, 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

FDSOI CMOS devices featuring dual strained channel and thin BOX extendable to the 10nm node

O. Faynot, Y. Escarabajal, B. Lherron, 2014, 2014 IEEE International Electron Devices Meeting.

A review of the mechanical stressors efficiency applied to the ultra-thin body & buried oxide fully depleted silicon on insulator technology

Pierre Morin, Sylvain Maitrejean, Frederic Allibert, 2016 .

Germanium-on-insulator (GeOI) structures realized by the Smart Cut technology

Frederic Allibert, N. Kernevez, Laurent Clavelier, 2004 .

High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET

M. Vinet, L. Grenouillet, T. Nagumo, 2012, 2012 International Electron Devices Meeting.

Germanium oxynitride (GeoxNy) as a back interface passivation layer for Germanium-on-insulator substrates

E. Augendre, T. Signamarcheix, L. Sanchez, 2008 .

150 mm SiC Engineered Substrates for High-Voltage Power Devices

Shawn G. Thomas, W. Schwarzenbach, J. Widiez, 2022, Materials Science Forum.

A mobility enhancement strategy for sub-14nm power-efficient FDSOI technologies

O. Rozeau, O. Faynot, G. Ghibaudo, 2014, 2014 IEEE International Electron Devices Meeting.

Fabrication and characterisation of 200 mm germanium-on-insulator (GeOI) substrates made from bulk germanium

T. Signamarcheix, L. Sanchez, F. Mazen, 2006 .

Characterization of Fully Silicided Source/Drain SOI UTBB nMOSFETs at Cryogenic Temperatures

J. Knoch, D. Grützmacher, S. Hoffmann‐Eifert, 2022, Solid-State Electronics.

Highly-Strained Silicon-On-Insulator Development

Christophe Figuet, Jean-Michel Hartmann, Chrystel Deguet, 2006 .