Tong Chen

发表

Scheduling for Clustered Vector Processors Near Memory

Bryan S. Rosenburg, S. Antão, A. Eichenberger, 2016 .

Preparation and optimization of a diverse workload for a large-scale heterogeneous system

Bronis R. de Supinski, John A. Gunnels, Yoonho Park, 2019, SC.

Using Structured Input and Modularity for Improved Learning pdf

Zehra Sura, Tong Chen, Hyojin Sung, 2019, ArXiv.

Data Dependence Profiling for Speculative Optimizations

Jin Lin, Wei-Chung Hsu, Pen-Chung Yew, 2004, CC.

Compiling ONNX Neural Network Models Using MLIR

Tung D. Le, Kiyokuni Kawachiya, A. Eichenberger, 2020, ArXiv.

Data access optimization in a processing-in-memory system

Yoonho Park, Kevin O'Brien, Zehra Sura, 2015, Conf. Computing Frontiers.

Active Memory Cube: A processing-in-memory architecture for exascale systems

Tejas Karkhanis, Chen-Yong Cher, John A. Gunnels, 2015, IBM J. Res. Dev..

Progressive Codesign of an Architecture and Compiler Using a Proxy Application

Kevin O'Brien, Zehra Sura, Tong Chen, 2015, 2015 27th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD).

Efficient Fork-Join on GPUs Through Warp Specialization

Tian Jin, Kevin O'Brien, Zehra Sura, 2017, 2017 IEEE 24th International Conference on High Performance Computing (HiPC).

Using advanced compiler technology to exploit the performance of the Cell Broadband EngineTM architecture

Michael Gschwind, Tao Zhang, Peng Wu, 2006, IBM Syst. J..

Automatic Loop Tiling for Direct Memory Access

Ling Shao, Tao Liu, Kevin O'Brien, 2011, 2011 IEEE International Parallel & Distributed Processing Symposium.

Implementing implicit OpenMP data sharing on GPUs

A. Eichenberger, Hyojin Sung, Gheorghe-Teodor Bercea, 2017, LLVM-HPC@SC.

Performance analysis of OpenMP on a GPU using a CORAL proxy application

Kevin O'Brien, Zehra Sura, Tong Chen, 2015, PMBS '15.

Coordinating GPU Threads for OpenMP 4.0 in LLVM

Kevin O'Brien, Zehra Sura, Tong Chen, 2014, 2014 LLVM Compiler Infrastructure in HPC.

HeapCheck: Low-cost Hardware Support for Memory Safety

A. Buyuktosunoglu, R. Boivie, Tong Chen, 2022, ACM Trans. Archit. Code Optim..

A compiler framework for speculative analysis and optimizations

Roy Dz-Ching Ju, Jin Lin, Wei-Chung Hsu, 2003, PLDI '03.

An Empirical Study on the Granularity of Pointer Analysis in C Programs

Jin Lin, Wei-Chung Hsu, Pen-Chung Yew, 2002, LCPC.

Hybrid access-specific software cache techniques for the cell BE architecture

Eduard Ayguadé, Tao Zhang, Kevin O'Brien, 2008, 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT).

Prefetching irregular references for software cache on cell

Tao Zhang, Zehra Sura, Marc González, 2008, CGO '08.

A Novel Asynchronous Software Cache Implementation for the Cell-BE Processor

Eduard Ayguadé, Tao Zhang, Kevin O'Brien, 2007, LCPC.

Designing the Agassiz Compiler for Concurrent Multithreaded Architectures

J. Liang, Jenn-Yuan Tsai, Pen-Chung Yew, 1999, LCPC.

Toward a progress indicator for program compilation

Tong Chen, Gang Luo, Hao Yu, 2007, Softw. Pract. Exp..

Hardware Support for Low-Cost Memory Safety

Gururaj Saileshwar, Tong Chen, Alper Buyuktosunoglu, 2021, 2021 51st Annual IEEE/IFIP International Conference on Dependable Systems and Networks - Supplemental Volume (DSN-S).