K. Richter

发表

Model composition for scheduling analysis in platform design

R. Ernst, K. Richter, D. Ziegenbein, 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

Transf ormation of SDL Specifications for System-Le vel Timing Anal ysis

R. Ernst, K. Richter, M. Jersak, 2002 .

Early Architecture Exploration with

R. Ernst, K. Richter, M. Jersak, 2004 .

Schedule Design to Guarantee Freedom of Interference in Mixed Criticality Systems

Christoph Ficek, Nico Feiertag, Kai Richter, 2012 .

Software Architecture Methods and Mechanisms for Timing Error and Failure Detection According to ISO 26262: Deadline vs. Execution Time Monitoring

Karsten Schmidt, Christoph Ficek, Nico Feiertag, 2013 .

Codesign of Embedded Systems-The SPI Workbench

L. Thiele, R. Ernst, K. Richter, 1999 .

Representation of process mode correlation for scheduling

L. Thiele, D. Ziegenbein, K. Richter, 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

System level performance analysis - the SymTA/S approach

Rolf Ernst, Kai Richter, Marek Jersak, 2005 .

Early Architecture Exploration with SymTA/S

Rolf Ernst, Kai Richter, Marek Jersak, 2005, MBEES.

Interval-based analysis in embedded system design

Rolf Ernst, Kai Richter, Marek Jersak, 2004, Math. Comput. Simul..

Scheduling analysis integration for heterogeneous multiprocessor SoC

Rolf Ernst, Kai Richter, Razvan Racu, 2003, RTSS 2003. 24th IEEE Real-Time Systems Symposium, 2003.

Event model interfaces for heterogeneous system analysis

Rolf Ernst, Kai Richter, R. Ernst, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

Calculating Task Output Event Models to Reduce Distributed System Cost

Rolf Ernst, Kai Richter, Razvan Racu, 2004, MBMV.

Breaking Down Complexity for Reliable System-Level Timing Validation

Kai Richter, Marek Jersak, Dirk Ziegenbein, 2002 .

Methods and Tools for End-to-End Latency Analysis and Optimization of a Dual-Processor Control Module

Kai Richter, Haibo Zeng, Arkadeb Ghosal, 2012 .

System Level Performance Analysis for Real-Time Automotive Multicore and Network Architectures

Rolf Ernst, Kai Richter, Simon Schliecker, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A framework for modular analysis and exploration of heterogeneous embedded systems

Rolf Ernst, Kai Richter, Marek Jersak, 2006, Real-Time Systems.

Design space exploration and system optimization with SymTA/S - symbolic timing analysis for systems

Rolf Ernst, Kai Richter, Marek Jersak, 2004, 25th IEEE International Real-Time Systems Symposium.

A Formal Approach to MpSoC Performance Verification

Rolf Ernst, Kai Richter, Marek Jersak, 2003, Computer.

System Level Performance Analysis for Real-Time

Rolf Ernst, Simon Schliecker, Kai Richter, 2009 .

SymTA/S - Symbolic Timing Analysis for Systems

Rolf Ernst, Kai Richter, Marek Jersak, 2004 .

A Formal Approach to MpSoC

Kai Richter, Marek Jersak, Rolf Ernst, 2003 .

A Compositional Framework for End-to-End Path Delay Calculation of Automotive Systems under Different Path Semantics

Nico Feiertag, Kai Richter, Johan Nordlander, 2008, RTSS 2009.

How Timing Interfaces in AUTOSAR can Improve Distributed Development of Real-Time Software

Nico Feiertag, Kai Richter, Oliver Scheickl, 2008, GI Jahrestagung.

On Managing Performance and Timing in Early-Stage E/E Design - Reducing the Gap Between Requirements and Implementation

Christoph Ficek, Nico Feiertag, Kai Richter, 2013 .

On Timing Requirements and a Critical Gap between Function Development and ECU Integration

Karsten Schmidt, Kai Richter, Denny Marx, 2015 .

Hierarchical Specification Methods for Platform-Based Design

Rolf Ernst, Kai Richter, Wayne Wolf, 2001 .

Flexibility/Cost-Tradeoffs of Platform-Based Systems

Christian Haubelt, Jürgen Teich, Rolf Ernst, 2002, Embedded Processor Design Challenges.

Automotive Software Integration

Rolf Ernst, Kai Richter, Arne Hamann, 2007, 2007 44th ACM/IEEE Design Automation Conference.

Bottom-Up Performance Analysis of HW/SW Platforms

Rolf Ernst, Kai Richter, Marek Jersak, 2002, DIPES.

Transformation of SDL specifications for system-level timing analysis

Rolf Ernst, Kai Richter, Marek Jersak, 2002, Proceedings of the Tenth International Symposium on Hardware/Software Codesign. CODES 2002 (IEEE Cat. No.02TH8627).

Combining complex event models and timing constraints

Rolf Ernst, Kai Richter, Marek Jersak, 2001, Sixth IEEE International High-Level Design Validation and Test Workshop.

Performance analysis for complex embedded applications

Rolf Ernst, Kai Richter, Marek Jersak, 2005, Int. J. Embed. Syst..

On the Decomposition of End-to-End Timing Requirements in Distributed Partitioned Automotive Functions

Christoph Ficek, Nico Feiertag, Kai Richter, 2012 .

Exploring Use of Ethernet for In-Vehicle Control Applications: AFDX, TTEthernet, EtherCAT, and AVB

Rolf Ernst, Kai Richter, Jonas Diemer, 2012 .