Zhiru Zhang

发表

System Synthesis and Automated Verification : Design Demands for IoT Devices

J. Cong, Deming Chen, W. Hwu, 2016 .

Experiences Using the RISC-V Ecosystem to Design an Accelerator-Centric SoC in TSMC 16nm

M. Taylor, R. Dreslinski, Rajesh K. Gupta, 2017 .

Bit-Level Transformation and Optimization for Hardware Synthesis of Algorithmic Descriptions

Mingxing Tan, J. Cong, Xu Cheng, 2009 .

Pilot – A Platform-Based HW / SW Synthesis System for FPSoC *

J. Cong, Zhiru Zhang, Yiping Fan, 2002 .

Architectural Specialization for Inter-Iteration Loop Dependence Patterns

Shreesha Srinath, Berkin Ilbeyi, Christopher Batten, 2014, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture.

XLOOPS : Explicit Loop Specialization

Mingxing Tan, C. Batten, Zhiru Zhang, 2014 .

Gradual relaxation techniques with applications to behavioral synthesis

J. Cong, M. Potkonjak, Zhiru Zhang, 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

Predictable accelerator design with time-sensitive affine types

Zhiru Zhang, Rachit Nigam, Sachille Atapattu, 2020, PLDI.

MGX: near-zero overhead memory protection for data-intensive accelerators

G. Suh, Zhiru Zhang, Weizhe Hua, 2020, ISCA.

GuardNN: secure accelerator architecture for privacy-preserving deep learning

G. Suh, Zhiru Zhang, Weizhe Hua, 2020, DAC.

SoftVN

G. Suh, Zhiru Zhang, Weizhe Hua, 2022, Proceedings of the 49th Annual International Symposium on Computer Architecture.

IMpress: Large Integer Multiplication Expression Rewriting for FPGA HLS

Cunxi Yu, Zhiru Zhang, Ismail San, 2022, 2022 IEEE 30th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

SoftVN: efficient memory protection via software-provided version numbers

G. Suh, Zhiru Zhang, Weizhe Hua, 2022, ISCA.

Enabling Design Methodologies and Future Trends for Edge AI: Specialization and Codesign

Luca Benini, Deming Chen, Jordan Dotzel, 2021, IEEE Design & Test.

TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design

Zhenman Fang, Yuze Chi, Linghao Song, 2022, ACM Trans. Reconfigurable Technol. Syst..

PokeBNN: A Binary Pursuit of Lightweight Accuracy

Yichi Zhang, Zhiru Zhang, Lukasz Lew, 2021, 2022 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR).

Understanding Hyperdimensional Computing for Parallel Single-Pass Learning

Christopher De Sa, Tao Yu, Zhiru Zhang, 2022, NeurIPS.

FPGA HLS Today: Successes, Challenges, and Opportunities

P. Pan, J. Cong, K. Vissers, 2022, ACM Trans. Reconfigurable Technol. Syst..

Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization pdf

Azadeh Davoodi, Zhiru Zhang, Sergio Bampi, 2020, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning

Evangeline F. Y. Young, Yuan Zhou, Zhiru Zhang, 2018, 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs

Rajesh Gupta, Zhiru Zhang, Mani B. Srivastava, 2017, FPGA.

High-Level Synthesis for FPGAs: From Prototyping to Deployment

Jason Cong, Zhiru Zhang, Bin Liu, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Decoupled Model Schedule for Deep Learning Training

Cody Hao Yu, Zhiru Zhang, Zhen Zhang, 2023, ArXiv.

An efficient and versatile scheduling algorithm based on SDC formulation

Jason Cong, Zhiru Zhang, J. Cong, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA

Jason Cong, Zhiru Zhang, Shih-Chieh Chang, 2008, 2008 Asia and South Pacific Design Automation Conference.

A Roadmap for Enabling a Future-Proof In-Network Computing Data Plane Ecosystem pdf

Srinivasan Seshan, James C. Hoe, Vyas Sekar, 2021, ArXiv.

GuardNN: Secure DNN Accelerator for Privacy-Preserving Deep Learning pdf

Zhiru Zhang, G. Edward Suh, Weizhe Hua, 2020, ArXiv.

MgX: Near-Zero Overhead Memory Protection with an Application to Secure DNN Acceleration pdf

Zhiru Zhang, G. Edward Suh, Muhammad Umar, 2020, ArXiv.

OverQ: Opportunistic Outlier Quantization for Neural Network Accelerators

Christopher De Sa, Zhiru Zhang, Ritchie Zhao, 2019, 1910.06909.

Overwrite Quantization: Opportunistic Outlier Handling for Neural Network Accelerators

Christopher De Sa, Zhiru Zhang, Ritchie Zhao, 2019, ArXiv.

MatRaptor: A Sparse-Sparse Matrix Multiplication Accelerator Based on Row-Wise Product

Nitish Srivastava, Zhiru Zhang, David Albonesi, 2020, 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

Tensaurus: A Versatile Accelerator for Mixed Sparse-Dense Tensor Computations

Nitish Srivastava, Hongbo Rong, Zhiru Zhang, 2020, 2020 IEEE International Symposium on High Performance Computer Architecture (HPCA).

Reverse Engineering Convolutional Neural Networks Through Side-channel Information Leaks

Zhiru Zhang, G. Edward Suh, Weizhe Hua, 2018, 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC).

Boosting the Performance of CNN Accelerators with Dynamic Fine-Grained Channel Gating

Zhiru Zhang, Christopher De Sa, G. Edward Suh, 2019, MICRO.

Dagger: efficient and fast RPCs in cloud microservices with near-memory reconfigurable NICs

Christina Delimitrou, Shaojie Xiang, Zhiru Zhang, 2021, ASPLOS.

Improving Neural Network Quantization without Retraining using Outlier Channel Splitting pdf

Zhiru Zhang, Christopher De Sa, Yuwei Hu, 2019, ICML.

High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS: A Case Study on SpMV

Yuwei Hu, Zhiru Zhang, Yixiao Du, 2022, FPGA.

GraphLily: Accelerating Graph Linear Algebra on HBM-Equipped FPGAs

Yuwei Hu, Ecenur Ustun, Zhiru Zhang, 2021, 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

Behavior-level observability don't-cares and application to low-power behavioral synthesis

Jason Cong, Zhiru Zhang, Bin Liu, 2009, ISLPED.

Analysis and Optimization of GNN-Based Recommender Systems on Persistent Memory

Yuwei Hu, Zhiru Zhang, Zhongming Yu, 2022, 2207.11918.

Benchmarking GNN-Based Recommender Systems on Intel Optane Persistent Memory

Yuwei Hu, Zhiru Zhang, Zhongming Yu, 2022, ArXiv.

Dense Pruning of Pointwise Convolutions in the Frequency Domain pdf

Adrian Sampson, Yuwei Hu, Mark Buckler, 2021, ArXiv.

Accurate Operation Delay Prediction for FPGA HLS Using Graph Neural Networks

Zhiru Zhang, Zhijing Li, Debjit Pal, 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations pdf

Zhiru Zhang, Deming Chen, Yichi Zhang, 2020, FPGA.

GraphZoom: A multi-level spectral approach for accurate and scalable graph embedding

Zhiru Zhang, Zhuo Feng, Chenhui Deng, 2019, ICLR.

Channel Gating Neural Networks

Zhiru Zhang, Christopher De Sa, G. Edward Suh, 2018, NeurIPS.

Structured Pruning is All You Need for Pruning CNNs at Initialization

Christopher De Sa, G. Suh, Yaohui Cai, 2022, ArXiv.

SPADE: A Spectral Method for Black-Box Adversarial Robustness Evaluation

Yaohui Cai, Zhiru Zhang, Zhuo Feng, 2021, ICML.

High-level Synthesis for Low-power Design

Zhiru Zhang, Deming Chen, Keith A. Campbell, 2015, IPSJ Trans. Syst. LSI Des. Methodol..

FeatGraph: A Flexible and Efficient Backend for Graph Neural Network Systems

Minjie Wang, Yuwei Hu, Mu Li, 2020, SC20: International Conference for High Performance Computing, Networking, Storage and Analysis.

A Scalable Approach to Exact Resource-Constrained Scheduling Based on a Joint SDC and SAT Formulation

Zhiru Zhang, Gai Liu, Steve Dai, 2018, FPGA.

PRIMAL: Power Inference using Machine Learning

Yuan Zhou, Zhiru Zhang, Brucek Khailany, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

T2S-Tensor: Productively Generating High-Performance Spatial Hardware for Dense Tensor Computations

Nitish Srivastava, Hongbo Rong, Guanyu Feng, 2019, 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

RapidStream: Parallel Physical Implementation of FPGA HLS Designs

J. Cong, Yuze Chi, Zhiru Zhang, 2022, FPGA.

AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs

Jason Cong, Yuze Chi, Ecenur Ustun, 2021, FPGA.

Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs

Yuan Zhou, Zhiru Zhang, Wenping Wang, 2018, FPGA.

Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks

David Z. Pan, Yibo Lin, Mingjie Liu, 2021, 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC).

Replication Package for Article: Predictable Accelerator Design with Time-Sensitive Affine types

Zhiru Zhang, Zhijing Li, Rachit Nigam, 2020, Artifact Digital Object Group.

Architecture and synthesis for multi-cycle communication

Jason Cong, Zhiru Zhang, Xun Yang, 2003, ISPD '03.

A Parallel Bandit-Based Approach for Autotuning FPGA Compilation

Zhiru Zhang, Chang Xu, Guojie Luo, 2017, FPGA.

SDC-based modulo scheduling for pipeline synthesis

Zhiru Zhang, Bin Liu, B. Liu, 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Challenges and opportunities of ESL design automation

Zhiru Zhang, Deming Chen, Deming Chen, 2012, 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology.

GARNET: Reduced-Rank Topology Learning for Robust and Scalable Graph Neural Networks

Zhiru Zhang, Zhuobo Feng, Xiuyu Li, 2022, LoG.

LAMDA: Learning-Assisted Multi-stage Autotuning for FPGA Design Closure

Zhiru Zhang, Cunxi Yu, Shaojie Xiang, 2019, 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

xPilot: A Platform-Based Behavioral Synthesis System

Jason Cong, Zhiru Zhang, Deming Chen, 2005 .

Building Efficient Deep Neural Networks With Unitary Group Convolutions

Zhiru Zhang, Christopher De Sa, Yuwei Hu, 2018, 2019 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR).

A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured Sparsity

Sai Kiran Cherupally, Zhiru Zhang, Jyotishman Saikia, 2023, IEEE Journal of Solid-State Circuits.

A 28nm 8-bit Floating-Point Tensor Core based CNN Training Processor with Dynamic Activation/Weight Sparsification

Sai Kiran Cherupally, Zhiru Zhang, Jyotishman Saikia, 2022, ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC).

Mapping-Aware Constrained Scheduling for LUT-Based FPGAs

Zhiru Zhang, Udit Gupta, Mingxing Tan, 2015, FPGA.

Exact Memory- and Communication-aware Scheduling of DNNs on Pipelined Edge TPUs

Cunxi Yu, Zhiru Zhang, Jiaqi Yin, 2022, 2022 IEEE/ACM 7th Symposium on Edge Computing (SEC).

Dagger: Towards Efficient RPCs in Cloud Microservices With Near-Memory Reconfigurable NICs

Christina Delimitrou, Zhiru Zhang, Shaojie Xiang, 2020, IEEE Computer Architecture Letters.

Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition

Jason Cong, Peng Wei, Ramesh Karri, 2021, 2021 Formal Methods in Computer Aided Design (FMCAD).

Towards Fast, Adaptive, and Hardware-Assisted User-Space Scheduling

David A. Koufaty, Christina Delimitrou, Ed Suh, 2023, arXiv.org.

Platform choices and design demands for IoT platforms: cost, power, and performance tradeoffs

Jason Cong, Zhiru Zhang, Deming Chen, 2016, IET Cyper-Phys. Syst.: Theory & Appl..

Dagger: Accelerating RPCs in Cloud Microservices Through Tightly-Coupled Reconfigurable NICs pdf

Christina Delimitrou, Shaojie Xiang, Zhiru Zhang, 2021, ArXiv.

Dagger: Efficient and Fast RPCs for Cloud Microservices with Near-Memory Reconfigurable NICs Extended Abstract

Christina Delimitrou, Zhiru Zhang, N. Lazarev, 2020 .

Painting on PIacement: Forecasting Routing Congestion using Conditional Generative Adversarial Nets

Zhiru Zhang, Cunxi Yu, Cunxi Yu, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

Platform-Based Behavior-Level and System-Level Synthesis

Jason Cong, Zhiru Zhang, Wei Jiang, 2006, 2006 IEEE International SOC Conference.

The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips

Christopher Torng, Christopher Batten, Ronald G. Dreslinski, 2018, IEEE Micro.

Precision Gating: Improving Neural Network Efficiency with Dynamic Dual-Precision Activations

G. Suh, Yichi Zhang, Zhiru Zhang, 2020, International Conference on Learning Representations.

Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency

Jason Cong, Cody Hao Yu, Zhe Chen, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing

Jason Cong, Cody Hao Yu, Yuan Zhou, 2019, FPGA.

Improving Neural Network Quantization using Outlier Channel Splitting

Zhiru Zhang, Christopher De Sa, Yuwei Hu, 2019 .

SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs

Jason Cong, Jie Wang, Yun Liang, 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs

Jason Cong, Zhiru Zhang, Deming Chen, 2007, 2007 Asia and South Pacific Design Automation Conference.

Instruction set extension with shadow registers for configurable processors

Jason Cong, Zhiru Zhang, Glenn Reinman, 2005, FPGA '05.

A reconfigurable analog substrate for highly efficient maximum flow computation

Zhiru Zhang, Gai Liu, Zhiru Zhang, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Architecture and compilation for data bandwidth improvement in configurable embedded processors

Jason Cong, Zhiru Zhang, Guoling Han, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

High-Level Synthesis with Timing-Sensitive Information Flow Enforcement

Zhiru Zhang, G. Edward Suh, Zhenghong Jiang, 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Architecture and Synthesis for Area-Efficient Pipelining of Irregular Loop Nests

Zhiru Zhang, Gai Liu, Ritchie Zhao, 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

ElasticFlow: A complexity-effective approach for pipelining irregular loop nests

Zhiru Zhang, Gai Liu, Ritchie Zhao, 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

FPGA-Based Real-Time Charged Particle Trajectory Reconstruction at the Large Hadron Collider

Zhiru Zhang, Robert Stone, Louise Skinnari, 2017, 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Application-specific instruction generation for configurable processor architectures

J. Cong, Zhiru Zhang, Yiping Fan, 2004, FPGA '04.

Slapo: A Schedule Language for Progressive Optimization of Large Deep Learning Model Training

Cody Hao Yu, Zhiru Zhang, Zhen Zhang, 2023, 2302.08005.

BulletTrain: Accelerating Robust Neural Network Training via Boundary Example Mining pdf

G. Edward Suh, Weizhe Hua, Zhiru Zhang, 2021, NeurIPS.

Flushing-enabled loop pipelining for high-level synthesis

Zhiru Zhang, Kecheng Hao, Mingxing Tan, 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

GuardNN: secure accelerator architecture for privacy-preserving deep learning

G. Suh, Zhiru Zhang, Weizhe Hua, 2020, DAC.

MGX: near-zero overhead memory protection for data-intensive accelerators

G. Suh, Zhiru Zhang, Weizhe Hua, 2020, ISCA.

ElasticFlow: A complexity-effective approach for pipelining irregular loop nests

Mingxing Tan, Zhiru Zhang, Steve Dai, 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

AutoPilot: A Platform-Based ESL Synthesis System

Jason Cong, Zhiru Zhang, Yiping Fan, 2008 .

Scheduling with integer time budgeting for low-power optimization

Jason Cong, Miodrag Potkonjak, Zhiru Zhang, 2008, 2008 Asia and South Pacific Design Automation Conference.

Dagger: Towards Efficient RPCs in Cloud Microservices With Near-Memory Reconfigurable NICs

Christina Delimitrou, Zhiru Zhang, N. Lazarev, 2020, IEEE Computer Architecture Letters.

Session details: Technical Session 5: Processors and Accelerators

Zhiru Zhang, Zhiru Zhang, 2015, Symposium on Field Programmable Gate Arrays.

Binarized Convolutional Neural Networks with Separable Filters for Efficient Hardware Acceleration

Zhiru Zhang, Mani B. Srivastava, Zhuowen Tu, 2017, 2017 IEEE Conference on Computer Vision and Pattern Recognition Workshops (CVPRW).