Debapriya Chatterjee

EQUIPE : Parallel Equivalence Checking with GPU ’ s

V. Bertacco, Debapriya Chatterjee, 2010 .

Hybrid checking for microarchitectural validation of microprocessor designs on acceleration platforms

Avi Ziv, Valeria Bertacco, Biruk Mammo, 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Addressing verification challenges of heterogeneous systems based on IBM POWER9

Klaus-Dieter Schubert, Krishnan Sugavanam, Aaron C. Brown, 2018, IBM J. Res. Dev..

ArChIVED : High Performance Validation of Microprocessors Using Event Digests

Chang-Hong Hsu, V. Bertacco, Ronny Morad, 2013 .

Approximating checkers for simulation acceleration

Avi Ziv, Valeria Bertacco, Biruk Mammo, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Harnessing Simulation Acceleration to Solve the Digital Design Verification Challenge

Debapriya Chatterjee, Debapriya Chatterjee, 2013 .

Gate-Level Simulation with GPU Computing

Valeria Bertacco, Andrew DeOrio, Debapriya Chatterjee, 2011, TODE.

ArChiVED: Architectural checking via event digests for high performance validation

Valeria Bertacco, Raviv Gal, Ronny Morad, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

High performance gate-level simulation with GP-GPU computing

Valeria Bertacco, Debapriya Chatterjee, V. Bertacco, 2011, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test.

Event-driven gate-level simulation with GP-GPUs

Valeria Bertacco, Andrew DeOrio, Debapriya Chatterjee, 2009, 2009 46th ACM/IEEE Design Automation Conference.

GCS: High-performance gate-level simulation with GPGPUs

Valeria Bertacco, Andrew DeOrio, Debapriya Chatterjee, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.