A. Agrawal

发表

A steep-slope transistor based on abrupt electronic phase transition

Arun V. Thathachary, S. Datta, A. Aziz, 2015, Nature Communications.

Study of TFET non-ideality effects for determination of geometry and defect density requirements for sub-60mV/dec Ge TFET

G. Dewey, B. Chu-Kung, J. Kavalieros, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Experimental Staggered-Source and N+ Pocket-Doped Channel III–V Tunnel Field-Effect Transistors and Their Scalabilities

Amy W. K. Liu, J. Fastenau, T. Mayer, 2011 .

In Situ Process Control of Trilayer Gate-Stacks on p-Germanium With 0.85-nm EOT

S. Datta, K. Ahmed, R. Engel-Herbert, 2015, IEEE Electron Device Letters.

Experimental Determination of Quantum and Centroid Capacitance in Arsenide–Antimonide Quantum-Well MOSFETs Incorporating Nonparabolicity Effect

J. B. Boos, S. Datta, B. R. Bennett, 2011, IEEE Transactions on Electron Devices.

300mm Heterogeneous 3D Integration of Record Performance Layer Transfer Germanium PMOS with Silicon NMOS for Low Power High Performance Logic Applications

G. Dewey, B. Chu-Kung, J. Kavalieros, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Fermi level depinning and contact resistivity reduction using a reduced titania interlayer in n-silicon metal-insulator-semiconductor ohmic contacts

Joyce C. Lin, S. Datta, R. White, 2014 .

Gate-All-Around Strained Si0.4Ge0.6 Nanosheet PMOS on Strain Relaxed Buffer for High Performance Low Power Logic Application

J. Kavalieros, M. Metz, A. Murthy, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

Heterogeneous integration of hexagonal boron nitride on bilayer quasi‐free‐standing epitaxial graphene and its impact on electrical transport properties

S. Datta, J. Robinson, D. Snyder, 2013 .

A unified model for insulator selection to form ultra-low resistivity metal-insulator-semiconductor contacts to n-Si, n-Ge, and n-InGaAs

S. Datta, K. Ahmed, N. Shukla, 2012 .

Barrier height reduction to 0.15eV and contact resistivity reduction to 9.1×10−9 Ω-cm2 using ultrathin TiO2−x interlayer between metal and silicon

S. Mohney, S. Chopra, A. Agrawal, 2013, Symposium on VLSI Technology.

Low-k interconnect stack with metal-insulator-metal capacitors for 22nm high volume manufacturing

K. Mistry, J. Hicks, P. Hentges, 2012, 2012 IEEE International Interconnect Technology Conference.