Guido Masera

发表

Guido Masera, G. Masera, 2005 .

Clock Distribution Network Optimization under Self-Heating and Timing Constraints

Gianluca Piccinini, Mariagrazia Graziano, Mario R. Casu, 2002, PATMOS.

A VLSI prolog processor, design and methodology: a case study in high level language processor design

Gianluca Piccinini, Guido Masera, Maurizio Zamboni, 1994 .

A Fast Design Space Exploration Framework for the Deep Learning Accelerators: Work-in-Progress

Guido Masera, Maurizio Martina, Alessio Colucci, 2020, 2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

A 50 Mbit/s iterative turbo-decoder

Massimo Ruo Roch, Gianluca Piccinini, Guido Masera, 2000, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537).

Low-Power Hardware Accelerator for Sparse Matrix Convolution in Deep Neural Network

Guido Masera, Maurizio Martina, Erik Anzalone, 2017, IIH-MSP.

Analysis on parallel implementations of fixed-complexity sphere decoder

Guido Masera, Bin Wu, 2011, Science China Information Sciences.

Design of Application Specific Processors for the Cached FFT Algorithm

Gerd Ascheid, Heinrich Meyr, Guido Masera, 2006, 2006 IEEE International Conference on Acoustics Speech and Signal Processing Proceedings.

Operation scheduling in VLSI circuit design

Gianluca Piccinini, Guido Masera, Maurizio Zamboni, 1994 .

Automotive Power-Line Communication Channels: Mathematical Characterization and Hardware Emulator

Paola Bisaglia, Guido Masera, Igor S. Stievano, 2016, IEEE Transactions on Industrial Electronics.

High Level Synthesis based FPGA Implementation of H.264/AVC Sub-Pixel Luma Interpolation Filters

Javed Iqbal, Guido Masera, Maurizio Martina, 2016, 2016 European Modelling Symposium (EMS).

Performance evaluation of a VLSI associative unifier in a WAM based environment

Gianluca Piccinini, Guido Masera, Maurizio Zamboni, 1991 .

Adaptive Approximated DCT Architectures for HEVC

Guido Masera, Maurizio Martina, G. Masera, 2017, IEEE Transactions on Circuits and Systems for Video Technology.

A Novel Architecture for Scalable, High Throughput, Multi-standard LDPC Decoder

Guido Masera, Ashwani Singh, Emmanuel Boutillon, 2011, 2011 14th Euromicro Conference on Digital System Design.

A Quantitative Approach to the Design of an Optimized Hardware Interpreter for Java Byte-Code

Massimo Ruo Roch, Gianluca Piccinini, Guido Masera, 1999, Applied Informatics.

A fast and accurate model for CMOS delays

Massimo Ruo Roch, Gianluca Piccinini, Mario R. Casu, 2000 .

A flexible encoder architecture for high throughput SeriallyConcatenated Convolutional Codes

Guido Masera, Maurizio Martina, 2007 .

VLSI Architecture for Low-Complexity Motion Estimation in H.264 Multiview Video Coding

Enrico Magli, Guido Masera, Maurizio Martina, 2013, 2013 Euromicro Conference on Digital System Design.

Parallel H.264/AVC Fast Rate-Distortion Optimized Motion Estimation by Using a Graphics Processing Unit and Dedicated Hardware

Enrico Magli, Guido Masera, Maurizio Martina, 2015, IEEE Transactions on Circuits and Systems for Video Technology.

A Flexible LDPC code decoder with a Network on Chip as underlying interconnect architecture pdf

Guido Masera, Carlo Condo, G. Masera, 2011, ArXiv.

A high accuracy-low complexity model for CMOS delays

Massimo Ruo Roch, Gianluca Piccinini, Mario R. Casu, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

Reconfigurable CDMA Receiver Architecture for 3G Mobile Terminals

Gianluca Piccinini, Guido Masera, Maurizio Zamboni, 2003 .

Embedded IWT evaluation in reconfigurable wireless sensor network

Gianluca Piccinini, Guido Masera, Maurizio Zamboni, 2002, 9th International Conference on Electronics, Circuits and Systems.

Hierarchical power supply noise evaluation for early power grid design prediction

Gianluca Piccinini, Mariagrazia Graziano, Guido Masera, 2001, SLIP '01.

Look-Ahead Sphere Decoding: Algorithm and performance evaluation

Micaela Troglia Gamba, Guido Masera, G. Masera, 2009, 2009 6th International Symposium on Wireless Communication Systems.

Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless Sensor

Gianluca Piccinini, Guido Masera, Maurizio Zamboni, 2002, FPL.

Silicon Compilation Approach for a VLSI Prolog Code Preprocessor Design

Massimo Ruo Roch, Gianluca Piccinini, Guido Masera, 1990 .

Complexity and implementation analysis of synthesized view distortion estimation architecture in 3D High Efficiency Video Coding

Guido Masera, Maurizio Martina, Waqar Ahmad, 2015, 2015 International Conference on 3D Imaging (IC3D).

An all-digital spike-based ultra-low-power IR-UWB dynamic average threshold crossing scheme for muscle force wireless transmission

Guido Masera, Marco Crepaldi, Danilo Demarchi, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

New 2 Gbit/s CMOS I/O pads

Massimo Ruo Roch, Gianluca Piccinini, Guido Masera, 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

Edge Computing: A Survey On the Hardware Requirements in the Internet of Things World

Massimo Ruo Roch, Guido Masera, Maurizio Martina, 2019, Future Internet.

VLSI Reed Solomon decoder architecture for networked multimedia applications

Gianluca Piccinini, Guido Masera, Maurizio Zamboni, 2001, Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558).

WindDesigner: An open tool for analysis and design of wind generators

Massimo Ruo Roch, Guido Masera, Giacomo Frulla, 2013, 2013 International Conference on Clean Electrical Power (ICCEP).

Implementation of a Flexible LDPC Decoder

Guido Masera, Fabrizio Vacca, Federico Quaglio, 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

Design of a VLSI Decoder for Partially Structured LDPC Codes

Guido Masera, Libero Dinoi, Fabrizio Vacca, 2008, Int. J. Digit. Multim. Broadcast..

Low-Complexity, Efficient 9/7 Wavelet Filters VLSI Implementation

Guido Masera, Maurizio Martina, G. Masera, 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

An electromigration and thermal model of power wires for a priori high-level reliability prediction

Gianluca Piccinini, Mariagrazia Graziano, Mario R. Casu, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Novel JPEG 2000 Compliant DWT and IWT VLSI Implementations

Gianluca Piccinini, Guido Masera, Maurizio Zamboni, 2003, J. VLSI Signal Process..

Comments on “Bitwise Log-Likelihood Ratios for Quadrature Amplitude Modulations”

Guido Masera, P. Takis Mathiopoulos, Maurizio Martina, 2015, IEEE Communications Letters.

A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization

Gianluca Piccinini, Mario R. Casu, Guido Masera, 2003, PATMOS.

Vlsi Implementation of WiMAX Convolutional Turbo Code Encoder and Decoder

Guido Masera, Maurizio Martina, Mario Nicola, 2009, J. Circuits Syst. Comput..

Testing logic cores using a BIST P1500 compliant approach: a case of study

Paolo Bernardi, Guido Masera, Matteo Sonza Reorda, 2005, Design, Automation and Test in Europe.

Primo: Reconfigurable Platform for Wideband WirelessCommunications

Gabriella Olmo, Guido Masera, Sergio Benedetto, 2004 .

A Parallel Implementation of LLR Generator for Soft-input Soft-output MIMO Detection

Bin Wu, Guido Masera, 2011 .

Beyond 3G wireless communication system prototype

Guido Masera, Mario Nicola, Alberto Dassatti, 2007, GLSVLSI '07.

Mumford and Shah functional: VLSI analysis and implementation

Guido Masera, Maurizio Martina, G. Masera, 2006, IEEE Transactions on Pattern Analysis and Machine Intelligence.

VLSI Implementation of a Multi-Mode Turbo/LDPC Decoder Architecture

Guido Masera, Maurizio Martina, Carlo Condo, 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

Effects of temperature in deep-submicron global interconnect optimization in future technology nodes

Gianluca Piccinini, Mariagrazia Graziano, Mario R. Casu, 2004, Microelectron. J..

Mixed hardware-software testbed for IEEE-802.11n

Guido Masera, Mario Nicola, Alberto Dassatti, 2006, 2nd International Conference on Testbeds and Research Infrastructures for the Development of Networks and Communities, 2006. TRIDENTCOM 2006..

High Speed Architectures for Finding the First two Maximum/Minimum Values

Luca Gaetano Amarù, Guido Masera, Maurizio Martina, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Algorithms for operation scheduling in VLSI circuit design

Gianluca Piccinini, Guido Masera, Maurizio Zamboni, 1993 .

Finite precision implementationof LDPC decoders

Guido Masera, Federico Quaglio, Fabrizio Vacca, 2005 .

Hardware and Software Optimizations for Accelerating Deep Neural Networks: Survey of Current Trends, Challenges, and the Road Ahead

Muhammad Shafique, Guido Masera, Alberto Marchisio, 2020, IEEE Access.

Noise-tolerance analysis for high speed CMOS circuits

Massimo Ruo Roch, Gianluca Piccinini, Mariagrazia Graziano, 1998, Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186).

Cell library development using multi-objective function optimization

Gianluca Piccinini, Guido Masera, Maurizio Zamboni, 2000, Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No.00TH8541).

Effects of Temperature in Deep-Submicron Global Interconnect Optimization

Gianluca Piccinini, Mariagrazia Graziano, Mario R. Casu, 2003, PATMOS.

Error correcting arithmetic coding for JPEG 2000: memory and performance analysis

Marco Grangetto, Guido Masera, Maurizio Martina, 2006, MobiMedia '06.

Scalable low-complexity B-spline discrete wavelet transform architecture

Gianluca Piccinini, Guido Masera, Maurizio Martina, 2010, IET Circuits Devices Syst..

FPGA accelerator of Quasi cyclic EG-LDPC codes decoder for NAND flash memories

Guido Masera, Maurizio Martina, Syed Azhar Ali Zaidi, 2013, 2013 Conference on Design and Architectures for Signal and Image Processing.

Real-time implementation of a time-frequency analysis scheme

Guido Masera, Maurizio Martina, Fabrizio Vacca, 2007, GLSVLSI '07.

Low Complexity, Flexible LDPC Decoders

Guido Masera, Fabrizio Vacca, Federico Quaglio, 2005 .

Power Control for Crossbar-Based Input-Queued Switches

Andrea Bianco, Paolo Giaccone, Guido Masera, 2013, IEEE Transactions on Computers.

Interconnection framework for high-throughput, flexible LDPC decoders

Guido Masera, Alberto Tarable, Fabrizio Vacca, 2006, Proceedings of the Design Automation & Test in Europe Conference.

A self-induced noise-tolerance measure structure for CMOS VLSI circuits

Gianluca Piccinini, Mariagrazia Graziano, Guido Masera, 1999 .

Flexible Architectures for LDPC Decoders Based on Network on Chip Paradigm

Amer Baghdadi, Guido Masera, Michel Jézéquel, 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

Decoding the Golden Code: A VLSI Design

Guido Masera, Emanuele Viterbo, Barbara Cerato, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Decoding the golden space-time trellis coded modulation

Guido Masera, Emanuele Viterbo, Barbara Cerato, 2008, IEEE Communications Letters.

Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-Advanced

Gianluca Piccinini, Guido Masera, Maurizio Martina, 2014, IEEE Signal Processing Letters.

LDPC check node implementation using reversible logic

Muhammad Awais, Guido Masera, Ashfaq Ahmed, 2019, IET Circuits Devices Syst..

Multiplierless Mumford and Shah Functional Implementation

Guido Masera, Maurizio Martina, G. Masera, 2011, Circuits Syst. Signal Process..

D21.3 Analysis of initial results at EuWIN@CTTC

Claude Oestges, Adrian Kliks, Pau Closas, 2014 .

Mixed hardware software testbed for 802.11n

Guido Masera, A. Poloni, Mario Nicola, 2006 .

A feasible VLSI engine for soft-input-soft-output for joint source channel codes

Guido Masera, Saeid Nooshabadi, Simone Zezza, 2009, 2009 16th IEEE International Conference on Image Processing (ICIP).

A parametrical architecture for Reed-Solomon decoders

Guido Masera, Mariana-Eugenia Petre, 1996, Proceedings of the Sixth Great Lakes Symposium on VLSI.

Transistors optimization of CMOS logic structures for high performance IC

Gianluca Piccinini, Mariagrazia Graziano, Guido Masera, 2000, ICM'99. Proceedings. Eleventh International Conference on Microelectronics (IEEE Cat. No.99EX388).

Considering microelectronics trends in advanced wireless system design

Dominique Noguet, Guido Masera, Marc Belleville, 2010 .

Synthesis of low-leakage PD-SOI circuits with body-biasing

Gianluca Piccinini, Mario R. Casu, Guido Masera, 2001, ISLPED '01.

On Practical Implementation and Generalizations of $ \max^{\ast}$ Operator for Turbo and LDPC Decoders

Guido Masera, P. Takis Mathiopoulos, Maurizio Martina, 2012, IEEE Transactions on Instrumentation and Measurement.

A flexible NoC-based LDPC code decoder implementation and bandwidth reduction methods

Guido Masera, Carlo Condo, G. Masera, 2011, Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP).

Coded 16-PSK: Effects of Imperfect Carrier Recovery and Resolution of Phase Ambiguities

Gabriella Olmo, Guido Masera, Sergio Benedetto, 1987 .

Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation

Frank Kienle, Amer Baghdadi, Christophe Moy, 2012, VLSI Design.

Reconfigurable coprocessor based JPEG 2000 implementation

Gianluca Piccinini, Guido Masera, Maurizio Zamboni, 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

An Updated Survey of Efficient Hardware Architectures for Accelerating Deep Convolutional Neural Networks

Muhammad Shafique, Guido Masera, Maurizio Martina, 2020, Future Internet.

Digital Circuits in a Multi-Functional SAGFET MMIC Technology

Mario R. Casu, Guido Masera, Maurizio Zamboni, 2000 .

JPEG2000 Decoder Architecture for Mobile Applications

Guido Masera, Maurizio Zamboni, Maurizio Martina, 2001 .

Rediscovering Logarithmic Diameter Topologies for Low Latency Network-on-Chip-Based Applications

Massimo Ruo Roch, Guido Masera, Maurizio Martina, 2014, 2014 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing.

Interconnection Structure for a Flexible LDPC Decoder

Guido Masera, Alberto Tarable, Fabrizio Vacca, 2006 .

ASIP design for partially structured LDPC codes

Guido Masera, Libero Dinoi, Fabrizio Vacca, 2006 .

A 2.63 Mbit/s VLSI Implementation of SISO Arithmetic Decoders for High Performance Joint Source Channel Codes

Guido Masera, Saeid Nooshabadi, Simone Zezza, 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

An Optimized Partial-Distortion-Elimination Based Sum-of-Absolute-Differences Architecture for High-Efficiency-Video-Coding

Muhammad Shafique, Guido Masera, Maurizio Martina, 2018, ApplePies.

FPGA superpipelined DSP core for 3G wireless applications

Gianluca Piccinini, Guido Masera, Maurizio Zamboni, 2002 .

Flexible blocks for high throughput serially concatenated convolutional codes

Guido Masera, Maurizio Martina, G. Masera, 2007, GLSVLSI '07.

X-TrainCaps: Accelerated Training of Capsule Nets through Lightweight Software Optimizations pdf

Muhammad Abdullah Hanif, Guido Masera, Maurizio Martina, 2019, ArXiv.

LISARM: embedded ARM platform design and optimization

Guido Masera, Fabrizio Vacca, Carlo Ceriani, 2007 .

An Eight-nodes-per-cycle Fixed-complexity Sphere Decoder in Complex Signal Model

Bin Wu, Guido Masera, 2011 .

High throughput implementation of an adaptive serial concatenation turbo decoder

Guido Masera, Maurizio Martina, Guido Montorsi, 2017 .

All digital VLSI fuzzy inference engine: a case study

Guido Masera, Danilo Demarchi, Pierluigi Civera, 1995 .

VLSI Prolog Processor, Design and Methodology

Gianluca Piccinini, Guido Masera, Maurizio Zamboni, 1994 .

Analysis of HEVC transform throughput requirements for hardware implementations

Guido Masera, Enrico Masala, Maurizio Martina, 2017, Signal Process. Image Commun..

A global optimization tool for CMOS logic circuits

Gianluca Piccinini, Mariagrazia Graziano, Guido Masera, 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357).

ALOE-Based Flexible LDPC Decoder

Guido Masera, Vuk Marojevic, Antoni Gelonch, 2010, 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools.

FFT implementation using QCA

Mariagrazia Graziano, Guido Masera, Marco Vacca, 2012, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012).

Log-MAP decoding of turbo codes and turbo trellis-coded modulation using piecewise-linear approximations of the max* operator

Guido Masera, P. Takis Mathiopoulos, Maurizio Martina, 2009 .

VLSI architectures for turbo codes

Massimo Ruo Roch, Gianluca Piccinini, Guido Masera, 1999, IEEE Trans. Very Large Scale Integr. Syst..

Hardware architecture for matrix factorization in mimo receivers

Guido Masera, Peter Nilsson, Barbara Cerato, 2007, GLSVLSI '07.

FPGA Architectures for Fast-Prunable Interleavers

Guido Masera, Maurizio Martina, Libero Dinoi, 2006 .

A High Speed Bit-serial 2d-DWT VLSI processor

Massimo Ruo Roch, Gianluca Piccinini, Guido Masera, 1998 .

Steerable-Discrete-Cosine-Transform (SDCT): Hardware Implementation and Performance Analysis †

Massimo Ruo Roch, Guido Masera, Maurizio Martina, 2020, Sensors.

Odd type DCT/DST for video coding: Relationships and low-complexity implementations

Guido Masera, Maurizio Martina, Maurizio Masera, 2017, 2017 IEEE International Workshop on Signal Processing Systems (SiPS).

High-speed Driven Technological Improvements Impact on InterconnectThermal Reliability in VLSI Circuits

Gianluca Piccinini, Mariagrazia Graziano, Mario R. Casu, 2001 .

Coupled electro-thermal modeling and optimization of clock networks

Gianluca Piccinini, Mariagrazia Graziano, Mario R. Casu, 2003, Microelectron. J..

A VLSI Decoder for the Golden code

Guido Masera, Emanuele Viterbo, Barbara Cerato, 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.

Optimized VLSI Architecture of HEVC Fractional Pixel Interpolators with Approximate Computing

Guido Masera, Luca Valente, Maurizio Martina, 2020, Journal of Low Power Electronics and Applications.

Approximate-Computing Architectures for Motion Estimation in HEVC

Muhammad Shafique, Guido Masera, Maurizio Martina, 2018, 2018 New Generation of CAS (NGCAS).

FasTrCaps: An Integrated Framework for Fast yet Accurate Training of Capsule Networks

Muhammad Shafique, Muhammad Abdullah Hanif, Guido Masera, 2020, 2020 International Joint Conference on Neural Networks (IJCNN).

Design and implementation of phase correlation based motion estimator

Guido Masera, Fabrizio Vacca, Andrea Molino, 2005, Proceedings 2005 IEEE International SOC Conference.

VLSI Architectures for WIMAX Channel Decoders pdf

Guido Masera, Maurizio Martina, G. Masera, 2009, ArXiv.

Turbo NOC: A Framework for the Design of Network-on-Chip-Based Turbo Decoder Architectures

Guido Masera, Maurizio Martina, G. Masera, 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

A Hardware Implementation for Code-based Post-quantum Asymmetric Cryptography

Guido Masera, Maurizio Martina, Marco Baldi, 2020, ITASEC.

Q-CapsNets: A Specialized Framework for Quantizing Capsule Networks

Muhammad Shafique, Guido Masera, Maurizio Martina, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

EE-BESD: molecular FET modeling for efficient and effective nanocomputing design

Mariagrazia Graziano, Guido Masera, Danilo Demarchi, 2016 .

Low-complexity, efficient 9/7 wavelet filters implementation

Guido Masera, Maurizio Martina, 2005, IEEE International Conference on Image Processing 2005.

Charge injection E/D MESFET structures for high speed and low power applications

Massimo Ruo Roch, Gianluca Piccinini, Guido Masera, 1998 .

A joint communication and application simulator for NoC-based SoCs pdf

Amer Baghdadi, Guido Masera, Carlo Condo, 2013, ArXiv.

Iterative MIMO detection: Flexibility and convergence analysis of Soft-Input Soft-Output List Sphere Decoding and Linear MMSE detection

Amer Baghdadi, Micaela Troglia Gamba, Guido Masera, 2010, SoftCOM 2010, 18th International Conference on Software, Telecommunications and Computer Networks.

Reducing the Dissipated Energy in Multi-standard Turbo and LDPC Decoders

Amer Baghdadi, Guido Masera, Carlo Condo, 2014, Circuits, Systems, and Signal Processing.

Reconfigurable DSP IP for multimedia applications

Gianluca Piccinini, Guido Masera, Maurizio Zamboni, 2002, 2002 IEEE International Conference on Acoustics, Speech, and Signal Processing.

Optimized CORDIC core for frequency-domain motion estimation

Guido Masera, Fabrizio Vacca, Andrea Molino, 2005, IEEE International Conference on Image Processing 2005.

Encoded 16-PSK: a study for the receiver design

Marco Ajmone Marsan, Gabriella Olmo, Guido Masera, 1989, IEEE J. Sel. Areas Commun..

State Metric Compression Techniques for Turbo Decoder Architectures

Guido Masera, Maurizio Martina, G. Masera, 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

FPGA implementation of time-frequency analysis algorithms for laser welding monitoring

Guido Masera, Maurizio Martina, Fabrizio Vacca, 2009, Microprocess. Microsystems.

A Joint Communication and Application Simulator for NoC-Based Custom SoCs: LDPC and Turbo Codes Parallel Decoding Case Study

Amer Baghdadi, Guido Masera, Carlo Condo, 2013, 2013 Euromicro Conference on Digital System Design.

FPGA Accelerator of Algebraic Quasi Cyclic LDPC Codes for nand Flash Memories

Guido Masera, Abuduwaili Tuoheti, Maurizio Martina, 2016, IEEE Design & Test.

Simplified Log-MAP Algorithm for Very Low-Complexity Turbo Decoder Hardware Architectures

Guido Masera, P. Takis Mathiopoulos, Maurizio Martina, 2014, IEEE Transactions on Instrumentation and Measurement.

Unequal Error Protection of Memories in LDPC Decoders

Guido Masera, Paolo Montuschi, Carlo Condo, 2015, IEEE Transactions on Computers.

VLSI Architectures for the Steerable-Discrete-Cosine-Transform (SDCT)

Massimo Ruo Roch, Guido Masera, Maurizio Martina, 2019, ApplePies.

Efficient Implementation Techniques for Maximum Likelihood-Based Error Correction for JPEG2000

Guido Masera, Saeid Nooshabadi, Maurizio Martina, 2009, IEEE Transactions on Circuits and Systems for Video Technology.

Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding

Luca Fanucci, Sergio Saponara, Guido Masera, 2010, Microprocess. Microsystems.

ISIS: a CAD tool for high speed VLSI design

Massimo Ruo Roch, Guido Masera, Maurizio Zamboni, 1998 .

A novel decoder architecture for error resilient JPEG2000 applications based on MQ arithmetic

Guido Masera, Saeid Nooshabadi, Simone Zezza, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

FPGA Fully Reconfigurable Lifting Kernel for Multimedia Processing

Gianluca Piccinini, Guido Masera, Maurizio Zamboni, 2001 .

A new performance evaluation metric for sub-optimal iterative decoders

Guido Masera, Ashwani Singh, Emmanuel Boutillon, 2009, IEEE Communications Letters.

System architecture for error-resilient, embedded JPEG2000 wireless delivery

Gianluca Piccinini, Guido Masera, Maurizio Zamboni, 2002, 2002 14th International Conference on Digital Signal Processing Proceedings. DSP 2002 (Cat. No.02TH8628).

Molecular transistor circuits: From device model to circuit simulation

Gianluca Piccinini, Mariagrazia Graziano, Guido Masera, 2014, 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

A Joint Source/Channel Approach to Strengthen Embedded Programmable Devices against Flash Memory Errors

Guido Masera, Maurizio Zamboni, Maurizio Martina, 2014, IEEE Embedded Systems Letters.

An LDPC Decoder Architecture for Wireless Sensor Network Applications

Guido Masera, Maurizio Martina, Andrea Dario Giancarlo Biroli, 2012, Sensors.

VLSI implementation of SISO arithmetic decoders for joint source channel coding

Guido Masera, Simone Zezza, 2008, 2008 Design, Automation and Test in Europe.

A Flexible UMTS-WiMax Turbo Decoder Architecture

Guido Masera, Maurizio Martina, Mario Nicola, 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

Low-Complexity Video Compression Combining Adaptive Multifoveation and Reuse of High-Resolution Information

Rashid Ansari, Guido Masera, Ashfaq A. Khokhar, 2006, 2006 International Conference on Image Processing.

Quantum Dot Cellular Automata Check Node Implementation for LDPC Decoders

Massimo Ruo Roch, Mariagrazia Graziano, Muhammad Awais, 2013, IEEE Transactions on Nanotechnology.

Hardware design of a low complexity, parallel interleaver for WiMax duo-binary turbo decoding

Guido Masera, Maurizio Martina, Mario Nicola, 2008, IEEE Communications Letters.

A parametric DCT architecture for H.263+ mobile terminals video streaming

Gianluca Piccinini, Guido Masera, Maurizio Zamboni, 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..

A PROLOG VLSI system for real time applications

Massimo Ruo Roch, Guido Masera, Pier Luigi Civera, 1995 .

Thermal Control for Crossbar-Based Input-Queued Switches

Andrea Bianco, Paolo Giaccone, Guido Masera, 2010, 2010 IEEE Global Telecommunications Conference GLOBECOM 2010.

Multiplierless, Folded 9/7– 5/3 Wavelet VLSI Architecture

Guido Masera, Maurizio Martina, G. Masera, 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

Reducing the memory for iteration-exchanged information and border future metrics in the HomePlug AV turbo decoder implementation

Paola Bisaglia, Guido Masera, Maurizio Martina, 2012, 2012 7th International Symposium on Turbo Codes and Iterative Information Processing (ISTC).

An Area-Efficient Variable-Size Fixed-Point DCT Architecture for HEVC Encoding

Guido Masera, Maurizio Martina, Maurizio Masera, 2020, IEEE Transactions on Circuits and Systems for Video Technology.

JPEG 2000: finite precision representation and hardware implications

Gianluca Piccinini, Guido Masera, Maurizio Zamboni, 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

High-Speed Logic Families Impact on Power Supply Noise Generation

Mariagrazia Graziano, Guido Masera, Maurizio Zamboni, 2001 .

Minimisation of control store width in digital systems

Gianluca Piccinini, Guido Masera, Maurizio Zamboni, 1994 .

Statistical Analysis of Power Supply Noise in Hierarchical Power Grid Networks

Massimo Ruo Roch, Gianluca Piccinini, Mariagrazia Graziano, 2003 .

A statistical model for estimating the effect of process variations on crosstalk noise

Guido Masera, Maurizio Martina, 2004, SLIP '04.

A set of design indep endent scripts for an incrementally selectable top-down or b ottom-upsynthesis strategy

Massimo Ruo Roch, Gianluca Piccinini, Mariagrazia Graziano, 2000 .

Turbo Decoder VLSI Architecture with Non-Recursive max* Operator for 3GPP LTE Standard

Guido Masera, Maurizio Martina, Ashfaq Ahmed, 2013 .

Architectural strategies for low-power VLSI turbo decoders

Gianluca Piccinini, Guido Masera, Maurizio Zamboni, 2002, IEEE Trans. Very Large Scale Integr. Syst..

A Novel VLSI Architecture of Fixed-Complexity Sphere Decoder

Guido Masera, Bin Wu, 2010, 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools.

VLSI Implementation of a Non-Binary Decoder Based on the Analog Digital Belief Propagation

Guido Masera, Maurizio Martina, Guido Montorsi, 2014, IEEE Transactions on Signal Processing.

Optimizing the transform complexity-quality tradeoff for hardware-accelerated HEVC video coding

Guido Masera, Enrico Masala, Maurizio Martina, 2015, 2015 Conference on Design and Architectures for Signal and Image Processing (DASIP).

A 650 MHz pipelined MAC for DSP applications using a new clocking strategy

Gianluca Piccinini, Guido Masera, Maurizio Zamboni, 1996, 1996 8th European Signal Processing Conference (EUSIPCO 1996).

Scalable, High Throughput LDPC Decoder for WiMAX (802.16e) Applications

Guido Masera, Ashwani Singh, Muhammad Awais, 2011, ACC.

Exploiting generalized de-Bruijn/Kautz topologies for flexible iterative channel code decoder architectures

Massimo Ruo Roch, Guido Masera, Maurizio Martina, 2015, Integr..

A high throughput turbo decoder VLSI architecture for 3GPP LTE standard

Muhammad Awais, Guido Masera, Ata ur Rehman, 2011, 2011 IEEE 14th International Multitopic Conference.

FFT processor: a case study in ASIP development

Gerd Ascheid, Heinrich Meyr, Guido Masera, 2005 .

Enabling VLSI Processing Blocks for MIMO-OFDM Communications

Guido Masera, Emanuele Viterbo, Barbara Cerato, 2008, VLSI Design.

A New Solution for Wireless Interactive TV Based on DVB-T Standard and SFDMA Technique

Guido Masera, P. Senn, Fabio Scalise, 1999 .

On the Effect of Approximate-Computing in Motion Estimation

Muhammad Shafique, Guido Masera, Maurizio Martina, 2019, J. Low Power Electron..

Hardware co-processors for Real-Time and High-Quality H.264/AVC video coding

Luca Fanucci, Sergio Saponara, Guido Masera, 2006, 2006 14th European Signal Processing Conference.

Error resilient JPEG2000 decoding for wireless applications

Guido Masera, Saeid Nooshabadi, Maurizio Martina, 2008, 2008 15th IEEE International Conference on Image Processing.

Power bus optimal sizing in presence of power supply noise

Gianluca Piccinini, Mariagrazia Graziano, Guido Masera, 2001, ICM 2001 Proceedings. The 13th International Conference on Microelectronics..

Approximate Arai DCT Architecture for HEVC

Guido Masera, Maurizio Martina, Giovanni Renda, 2017, 2017 New Generation of CAS (NGCAS).

A low power architecture for AER event-processing microcontroller

Guido Masera, Paolo Motto Ros, Maurizio Martina, 2017, 2017 IEEE Biomedical Circuits and Systems Conference (BioCAS).

A Prototype VLSI solution for Digital Terrestrial TV receivers, according toDVB-T standard

Guido Masera, P. Penard, P. Combelles, 1997 .

Reliability in VLSI Circuits

Gianluca Piccinini, Mariagrazia Graziano, Mario R. Casu, 2001 .

Noise safety design methodologies

Gianluca Piccinini, Mariagrazia Graziano, Guido Masera, 2000, Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525).

On chip interconnects for multiprocessor turbo decoding architectures

Amer Baghdadi, Guido Masera, Maurizio Martina, 2011, Microprocess. Microsystems.

Unified turbo/LDPC code decoder architecture for deep-space communications

Guido Masera, Carlo Condo, G. Masera, 2014, IEEE Transactions on Aerospace and Electronic Systems.

A new approach to compress the configuration information of programmable devices

Guido Masera, Massimo Violante, Luca Sterpone, 2006, Proceedings of the Design Automation & Test in Europe Conference.

An application specific instruction set processor based implementation for signal detection in multiple antenna systems

Guido Masera, Maurizio Martina, M. Tamagnone, 2012, Microprocess. Microsystems.

A CAD tool for noise tolerance analysis of CMOS digital circuits

Massimo Ruo Roch, Gianluca Piccinini, Mariagrazia Graziano, 1998 .

Improving Network-on-Chip-based Turbo Decoder Architectures

Guido Masera, Maurizio Martina, G. Masera, 2011, J. Signal Process. Syst..

Power Supply Design Parameters for Switching-Noise Control in Deep-Submicron Circuits Design Flows

Gianluca Piccinini, Mariagrazia Graziano, Guido Masera, 2002 .

Efficient VLSI implementation of soft-input soft-output fixed-complexity sphere decoder

Guido Masera, Bin Wu, G. Masera, 2012, IET Commun..

A Network-on-Chip-based turbo/LDPC decoder architecture

Guido Masera, Maurizio Martina, Carlo Condo, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Automated power supply noise reduction via optimized distributed capacitors insertion

Gianluca Piccinini, Mariagrazia Graziano, Guido Masera, 2001, 2001 Southwest Symposium on Mixed-Signal Design (Cat. No.01EX475).

Look-ahead sphere decoding: algorithm and VLSI architecture

Micaela Troglia Gamba, Guido Masera, G. Masera, 2011, IET Commun..

A CMOS Power Delay Model

Massimo Ruo Roch, Gianluca Piccinini, Guido Masera, 1999 .

On the Decoding of LDPC Codes in Finite-Precision Arithmetics

Luca Fanucci, Guido Masera, Massimo Rovini, 2006 .

Reconfigurable HW implementation of an OFDM baseband transceiver

Guido Masera, Mario Nicola, Fabrizio Vacca, 2006 .

Chapter 13 – Hardware Design and Realization for Iteratively Decodable Codes

Guido Masera, Emmanuel Boutillon, E. Boutillon, 2014 .

MP-SoC/NoC Architectures for Error Correction

Guido Masera, Maurizio Martina, Carlo Condo, 2015 .

A Multi-Kernel Multi-Code Polar Decoder Architecture

Guido Masera, Warren J. Gross, Carlo Condo, 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

The ultimate limits of wireless networks

Yonina C. Eldar, Shlomo Shamai, Guido Masera, 2012 .

Energy-efficient multi-standard early stopping criterion for low-density-parity-check iterative decoding

Amer Baghdadi, Guido Masera, Carlo Condo, 2014, IET Commun..

A System View on Iterative MIMO Detection: Dynamic Sphere Detection versus Fixed Effort List Detection

Frank Kienle, Guido Masera, Bin Wu, 2012, VLSI Design.

PRIMO: Reconfigurable Platforms fro Wideband Wireless Communications

Gabriella Olmo, Guido Masera, Sergio Benedetto, 2004 .

Architectural Strategies for Low-Power

Guido Masera, Maurizio Zamboni, Gianluca Piccinini, 2002 .

A Parallel Radix-Sort-Based VLSI Architecture for Finding the First $W$ Maximum/Minimum Values

Gianluca Piccinini, Guido Masera, Maurizio Martina, 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

An Experimental Multi-processor System for OR-parallel Prolog Execution

Gianluca Piccinini, Guido Masera, Maurizio Zamboni, 1989 .

VLSI architectures for iterative decoding of concatenated codes with interleavers

Massimo Ruo Roch, Gianluca Piccinini, Guido Masera, 1997 .

A Parallel Inference Machine for Automotive Applications

Gianluca Piccinini, Guido Masera, Maurizio Zamboni, 1990 .

Low-Complexity Reconfigurable DCT-V Architecture

Massimo Ruo Roch, Guido Masera, Maurizio Martina, 2020, IEEE Transactions on Circuits and Systems II: Express Briefs.

Heterogeneous and opportunistic wireless networks

Yonina C. Eldar, Shlomo Shamai, Jordi Pérez-Romero, 2012 .

Corrections to "Multiplierless, Folded 9/7-5/3 Wavelet VLSI Architecture" [Sep 07 770-774]

Guido Masera, Maurizio Martina, 2008, IEEE Trans. Circuits Syst. II Express Briefs.

Enabling “hard” technologies for future wireless

Dominique Noguet, Christophe Moy, Guido Masera, 2012 .

A 500 MHz 2d-DWT VLSI processor

Massimo Ruo Roch, Gianluca Piccinini, Guido Masera, 1998, 9th European Signal Processing Conference (EUSIPCO 1998).

Non-recursive max* operator with reduced implementation complexity for turbo decoding

Guido Masera, P. Takis Mathiopoulos, Maurizio Martina, 2012, IET Commun..

On optimal and near-optimal turbo decoding using generalized max operator

Guido Masera, P. Takis Mathiopoulos, Maurizio Martina, 2009, IEEE Communications Letters.

Efficient Operation Scheduling in Successive-Cancellation-based polar decoders

Guido Masera, Warren J. Gross, Carlo Condo, 2018, 2018 IEEE International Workshop on Signal Processing Systems (SiPS).

Flexible hardware for wireless communications: a case of study

Guido Masera, 2005 .

High performance channel model hardware emulator for 802.11n

Guido Masera, Mario Nicola, Alberto Dassatti, 2005, Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005..

Comparison between HEVC and Thor based on objective and subjective assessments

Guido Masera, Maurizio Martina, Paola Sunna, 2016, 2016 International Conference on Systems, Signals and Image Processing (IWSSIP).

Switching noise analysis framework for high speed logic families

Gianluca Piccinini, Mariagrazia Graziano, Guido Masera, 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.

PROXIMA: un Processore CMOS per l'esecuzione compilata di Prolog

Gianluca Piccinini, Guido Masera, Maurizio Zamboni, 1989 .

Design and implementation of a scalable multimedia processor

Gianluca Piccinini, Guido Masera, Maurizio Zamboni, 2003, IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings..

Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT

Massimo Ruo Roch, Gianluca Piccinini, Guido Masera, 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

A noise test structure for CMOS logic families

Gianluca Piccinini, Mariagrazia Graziano, Guido Masera, 2000, ICM'99. Proceedings. Eleventh International Conference on Microelectronics (IEEE Cat. No.99EX388).

REDUCED COMPLEXITY ALGORITHMS FOR NEAR-OPTIMAL DECODING OF TURBO AND TURBO TCM CODES

Guido Masera, P. Takis Mathiopoulos, Maurizio Martina, 2009 .

Interconnection Framework for High-Throughput LDPC Decoders

Guido Masera, Alberto Tarable, Fabrizio Vacca, 2006 .

R-SNN: An Analysis and Design Methodology for Robustifying Spiking Neural Networks against Adversarial Attacks through Noise Filters for Dynamic Vision Sensors

Guido Masera, Maurizio Martina, Alberto Marchisio, 2021, 2021 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS).

Custom Memory Design for Logic-in-Memory: Drawbacks and Improvements over Conventional Memories

Guido Masera, Giovanna Turvani, Marco Vacca, 2021, Electronics.

CarSNN: An Efficient Spiking Neural Network for Event-Based Autonomous Cars on the Loihi Neuromorphic Research Processor

Guido Masera, Maurizio Martina, Alberto Marchisio, 2021, 2021 International Joint Conference on Neural Networks (IJCNN).

Efficient Hardware Implementation of the LEDAcrypt Decoder

Guido Masera, Marco Baldi, Franco Chiaraluce, 2021, IEEE Access.