Szu-Tsung Cheng

VIS: A System for Verification and Synthesis

Tiziano Villa, Stephen A. Edwards, Szu-Tsung Cheng, 1996, CAV.

VIS

R. Brayton, A. Sangiovanni-Vincentelli, G. Hachtel, 2021 .

Compiling Verilog into Automata

Szu-Tsung Cheng, Szu-Tsung Cheng, 1994 .

HSIS: A BDD-Based Environment for Formal Verification

Szu-Tsung Cheng, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli, 1994, 31st Design Automation Conference.

Compilation, synthesis, and simulation of hardware description languages: the compositional models of hdl's

Szu-Tsung Cheng, Robert K. Brayton, R. Brayton, 1998 .

Compiling Verilog into timed finite state machines

R. Brayton, K. Yelick, A. Saldanha, 1995, Proceedings. 1995 IEEE International Verilog HDL Conference.

Synthesizing multi-phase HDL programs

Szu-Tsung Cheng, Robert K. Brayton, R. Brayton, 1996, Proceedings. IEEE International Verilog HDL Conference.

Parallelism and locality in priority queues

Szu-Tsung Cheng, Abhiram G. Ranade, Jeff A. Jones, 1994, Proceedings of 1994 6th IEEE Symposium on Parallel and Distributed Processing.