Che-Hua Shih

On compliance test of on-chip bus for SOC

Jing-Yang Jou, Hue-Min Lin, Chia-Chih Yen, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

Automatic Verification Stimulus Generation for Interface Protocols Modeled With Non-Deterministic Extended FSM

Jing-Yang Jou, Juinn-Dar Huang, Che-Hua Shih, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

FSM-based transaction-level functional coverage for interface compliance verification

Jing-Yang Jou, Juinn-Dar Huang, Che-Hua Shih, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Accelerating dynamic peak power analysis using an essential-signal-based methodology

Chia-Chih Yen, Hermes Lin, Jing-Yang Jou, 2011, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test.

FSM-Based Formal Compliance Verification of Interface Protocols

Chia-Chih Yen, Jing-Yang Jou, Juinn-Dar Huang, 2010, J. Inf. Sci. Eng..

An efficient approach for error diagnosis in HDL design

Jing-Yang Jou, Che-Hua Shih, Jing-Yang Jou, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

Equivalence checking of scheduling with speculative code transformations in high-level synthesis

Jing-Yang Jou, Juinn-Dar Huang, Che-Hua Shih, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).