A. Makihara

发表

Hardness-by-design approach for 0.15 /spl mu/m fully depleted CMOS/SOI digital logic devices with enhanced SEU/SET immunity

S. Matsuda, S. Kuboyama, H. Shindou, 2005, IEEE Transactions on Nuclear Science.

Analysis of single-ion multiple-bit upset in high-density DRAMs

Sumio Matsuda, A. B. Campbell, N. Nemoto, 2000 .

A nondamaging beam blanking SEM test method and its application to highly integrated devices

S. Matsuda, S. Kuboyama, A. Makihara, 2001 .

DICE-Based Flip-Flop With SET Pulse Discriminator on a 90 nm Bulk CMOS Process

S. Kuboyama, H. Shindou, T. Hirao, 2010, IEEE Transactions on Nuclear Science.