P. Zipf

发表

Constant Matrix Multiplication with Ternary Adders

Peter Zipf, Martin Kumm, Patrick Sittel, 2018, 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

HatScheT : A Contribution to Agile HLS

A. Koch, M. Kumm, Patrick Sittel, 2018 .

On a hardware architecture for the evolution of cellular automata functionality

M. Glesner, R. Dogaru, P. Zipf, 2005, International Symposium on Signals, Circuits and Systems, 2005. ISSCS 2005..

Design Optimisations for a Cellular Automata Model with Programmable Interconnect Structure

Lei Liu, Zdravko Bozakov, Peter Zipf, 2007 .

Dynamically Reconfigurable Computing for Wireless Communication Systems

Peter Zipf, Manfred Glesner, Heiko Hinkelmann, 2007 .

An asynchronous switch implementation for systems-on-a-chip

Peter Zipf, Manfred Glesner, Thomas Hollstein, 2004 .

Real-time fetal ECG system design using embedded microprocessors

Uwe Meyer-Baese, Peter Zipf, Martin Kumm, 2016, Commercial + Scientific Sensing and Imaging.

Arbitrary function approximation in HDLs with application to the N-body problem

Philip Heng Wai Leong, Alberto García Ortiz, Manfred Glesner, 2003, Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798).

Fly - A Modifiable Hardware Compiler

Philip Heng Wai Leong, Alberto García Ortiz, Manfred Glesner, 2002, FPL.

Unrolling Ternary Neural Networks

Peter Zipf, Martin Kumm, David Boland, 2019, ACM Trans. Reconfigurable Technol. Syst..

Efficient Error-Tolerant Quantized Neural Network Accelerators

Martin Kumm, Peter Zipf, Michaela Blott, 2019, 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

Pipelined compressor tree optimization using integer linear programming

Peter Zipf, Martin Kumm, M. Kumm, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

Optimal Single Constant Multiplication Using Ternary Adders

Peter Zipf, Martin Kumm, Oscar Gustafsson, 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

Optimization of Constant Matrix Multiplication with Low Power and High Throughput

Peter Zipf, Martin Kumm, Martin Hardieck, 2017, IEEE Transactions on Computers.

Reconfigurable Constant Multiplication for FPGAs

Peter Zipf, Martin Kumm, Konrad Möller, 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

High-Level Synthesis for Model-Based Design with Automatic Folding including Combined Common Subcircuits

Peter Zipf, Martin Kumm, Patrick Sittel, 2017, MBMV.

FIR filter optimization for video processing on FPGAs

D. Fanghänel, U. Meyer-Bäse, M. Kumm, 2013, EURASIP J. Adv. Signal Process..

FIR filter optimization for video processing on

Uwe Meyer-Baese, Peter Zipf, Diana Fanghänel, 2013 .

Isomorphic Subgraph-based Problem Reduction for Resource Minimal Modulo Scheduling

Martin Kumm, Peter Zipf, Patrick Sittel, 2019, 2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig).

Implementation of Realtime and Highspeed Phase Detector on FPGA

Manfred Glesner, Peter Zipf, Martin Kumm, 2006, ARC.

On the design of reconfigurable multipliers for integer and Galois field multiplication

Manfred Glesner, Peter Zipf, Jia Li, 2009, Microprocess. Microsystems.

Reconfigurable platforms for ubiquitous computing

Leandro Soares Indrusiak, Manfred Glesner, Tudor Murgan, 2004, CF '04.

A hardware-in-the-loop system to evaluate the performance of small-world cellular automata

Radu Dogaru, Manfred Glesner, Clemens Schlachta, 2005, International Conference on Field Programmable Logic and Applications, 2005..

2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), Darmstadt, Germany, July 10-12, 2013

Leandro Soares Indrusiak, Kartikeya Bhardwaj, Pravin S. Mane, 2013, Reconfigurable Communication-centric Systems-on-Chip.

The XPP Architecture and Its Co-simulation Within the Simulink Environment

Manfred Glesner, Tudor Murgan, Mihail Petrov, 2004, FPL.

AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers

Peter Zipf, Martin Kumm, Philip H. W. Leong, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An Efficient Softcore Multiplier Architecture for Xilinx FPGAs

Peter Zipf, Martin Kumm, Shahid Abbas, 2015, 2015 IEEE 22nd Symposium on Computer Arithmetic.

Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream

Michel Renovell, Peter Zipf, Manfred Glesner, 2002, Lecture Notes in Computer Science.

Systems on a Chip

Manfred Glesner, Peter Zipf, M. Glesner, 2004 .

Current Status and Future Perspectives

Peter Zipf, Manfred Glesner, M. Glesner, 2004 .

A configurable pipelined state machine as a hybrid ASIC and configurable architecture

Manfred Glesner, Peter Zipf, Claude Stötzler, 2004, IEEE Computer Society Annual Symposium on VLSI.

A Decentralised Task Mapping Approach for Homogeneous Multiprocessor Network-On-Chips

Pascal Benoit, Manfred Glesner, Peter Zipf, 2009, Int. J. Reconfigurable Comput..

A hierarchical generic approach for on-chip communication, testing and debugging of SoCs

Manfred Glesner, Peter Zipf, Christoph Mager, 2003, VLSI-SOC.

Generation of Synthetic Floating-Point benchmark circuits

Philip Heng Wai Leong, Manfred Glesner, Peter Zipf, 2009, 2009 IEEE International Symposium on Parallel & Distributed Processing.

Applying Dynamic Reconfiguration for Fault Tolerance in Fine-Grained Logic Arrays

Peter Zipf, P. Zipf, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

SPP1148 booth: Coarse-grained reconfiguration

Jürgen Teich, Julio A. de Oliveira Filho, Wolfgang Rosenstiel, 2008, 2008 International Conference on Field Programmable Logic and Applications.