Narayanan Vijaykrishnan

发表

Staggered latch bus: A reliable offset switched architecture for long on-chip interconnect

Narayanan Vijaykrishnan, Melvin Eze, Ozcan Ozturk, 2013, 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC).

Reconfigurable BDD based quantum circuits

Narayanan Vijaykrishnan, Soumya Eachempati, Vinay Saripalli, 2008, 2008 IEEE International Symposium on Nanoscale Architectures.

Tunnel FET RF Rectifier Design for Energy Harvesting Applications

Narayanan Vijaykrishnan, Xueqing Li, Suman Datta, 2014, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Exploiting Heterogeneity for Energy Efficiency in Chip Multiprocessors

Narayanan Vijaykrishnan, Yuan Xie, Vinay Saripalli, 2011, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Design of a nanosensor array architecture

Narayanan Vijaykrishnan, Mary Jane Irwin, Wei Xu, 2004, GLSVLSI '04.

Context-Aware Convolutional Neural Network over Distributed System in Collaborative Computing

Narayanan Vijaykrishnan, Jinhang Choi, Zeinab Hakimi, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

The design and use of simplePower: a cycle-accurate energy estimation tool

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2000, Proceedings 37th Design Automation Conference.

Analysis and solutions to issue queue process variation

Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam, 2008, 2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN).

Going Vertical: The Future of Electronics

Narayanan Vijaykrishnan, N. Vijaykrishnan, 2019, IEEE Micro.

Mixed Precision Quantization Scheme for Re-configurable ReRAM Crossbars Targeting Different Energy Harvesting Scenarios

Narayanan Vijaykrishnan, Keni Qiu, Changchi Shuai, 2019, IFIPIoT.

Process-Variation-Aware Adaptive Cache Architecture and Management

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2009, IEEE Transactions on Computers.

Comparative Area and Parasitics Analysis in FinFET and Heterojunction Vertical TFET Standard Cells

Narayanan Vijaykrishnan, Xueqing Li, Jack Sampson, 2016, ACM J. Emerg. Technol. Comput. Syst..

- Compiler-Directed Communication Energy Optimizations for Microsensor Networks

Narayanan Vijaykrishnan, Mary Jane Irwin, Alok Choudhary, 2012 .

Network-on-Chip Architectures - A Holistic Design Exploration

Chita R. Das, Narayanan Vijaykrishnan, Chrysostomos Nicopoulos, 2010, Lecture Notes in Electrical Engineering.

The substrate noise detector for noise tolerant mixed-signal IC

Narayanan Vijaykrishnan, Mary Jane Irwin, Byung-Tae Kang, 2003, IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings..

OS-Aware Branch Prediction: Improving Microprocessor Control Flow Prediction for Operating Systems

Narayanan Vijaykrishnan, Anand Sivasubramaniam, Lizy Kurian John, 2007, IEEE Transactions on Computers.

Thermal-aware reliability analysis for Platform FPGAs

Narayanan Vijaykrishnan, Yuan Xie, Sungmin Bae, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

Evaluating alternative implementations for LDPC decoder check node function

Narayanan Vijaykrishnan, Mary Jane Irwin, Theocharis Theocharides, 2004, IEEE Computer Society Annual Symposium on VLSI.

A Scalable Bandwidth-Aware Architecture for Connected Component Labeling

Narayanan Vijaykrishnan, Vikram Sampath Kumar, Kevin M. Irick, 2010, ISVLSI.

Reducing leakage energy in FPGAs using region-constrained placement

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2004, FPGA '04.

Simultaneous memory and bus partitioning for SoC architectures

Luca Benini, Narayanan Vijaykrishnan, Federico Angiolini, 2005, Proceedings 2005 IEEE International SOC Conference.

Incidental Computing on IoT Nonvolatile Processors

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Yuan Xie, 2017, 2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

LATTE: Low-power Audio Transform with TrueNorth Ecosystem

Narayanan Vijaykrishnan, Andrew S. Cassidy, Alexander Andreopoulos, 2016, 2016 International Joint Conference on Neural Networks (IJCNN).

Morphable Cache Architectures: Potential Benefits

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2001, LCTES/OM.

A holistic approach to designing energy-efficient cluster interconnects

Mahmut T. Kandemir, Chita R. Das, Narayanan Vijaykrishnan, 2005, IEEE Transactions on Computers.

Rf-powered systems using steep-slope devices

Narayanan Vijaykrishnan, Xueqing Li, Suman Datta, 2014, 2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS).

Variation-aware task allocation and scheduling for MPSoC

Narayanan Vijaykrishnan, Xiaoxia Wu, Yuan Xie, 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

A Multitask Grocery Assist System for the Visually Impaired: Smart glasses, gloves, and shopping carts provide auditory and tactile feedback

Narayanan Vijaykrishnan, Suman Datta, Jack Sampson, 2017, IEEE Consumer Electronics Magazine.

Exploiting VLIW schedule slacks for dynamic and leakage energy reduction

Wei Zhang, Mahmut T. Kandemir, Narayanan Vijaykrishnan, 2001, MICRO.

An Energy-Aware Approach for Sensor Data Communication

Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut Kandemir, 2012 .

Editorial

Narayanan Vijaykrishnan, 2008, ACM J. Emerg. Technol. Comput. Syst..

Embedded hardware face detection

Narayanan Vijaykrishnan, Mary Jane Irwin, Theocharis Theocharides, 2004, 17th International Conference on VLSI Design. Proceedings..

Harnessing ferroelectrics for non-volatile memories and logic

Narayanan Vijaykrishnan, Xueqing Li, Suman Datta, 2017, 2017 18th International Symposium on Quality Electronic Design (ISQED).

Accurate stacking effect macro-modeling of leakage power in sub-100 nm circuits

Narayanan Vijaykrishnan, Yuan Xie, Wenping Wang, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers

Chita R. Das, Narayanan Vijaykrishnan, Jongman Kim, 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

Design and analysis of an NoC architecture from performance, reliability and energy perspective

Chita R. Das, Narayanan Vijaykrishnan, Jongman Kim, 2008 .

Impact of technology scaling and packaging on dynamic voltage scaling techniques

Narayanan Vijaykrishnan, Mary Jane Irwin, D. Duarte, 2002, 15th Annual IEEE International ASIC/SOC Conference.

Compiler optimizations for low power systems

Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut Kandemir, 2002 .

Architecture and Design Flow Optimizations for Power-Aware FPGAs

Narayanan Vijaykrishnan, Aman Gayasen, 2006 .

On load latency in low-power caches

Narayanan Vijaykrishnan, Mary Jane Irwin, Lizy Kurian John, 2003, ISLPED '03.

A GPU based implementation of Center-Surround Distribution Distance for feature extraction and matching

Narayanan Vijaykrishnan, Robert T. Collins, Weina Ge, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

An Exploration of Hardware Architectures for Face Detection

Narayanan Vijaykrishnan, Mary Jane Irwin, Theocharis Theocharides, 2006 .

Thermal-Aware Application Scheduling on Device-Heterogeneous Embedded Architectures

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Huichu Liu, 2015, 2015 28th International Conference on VLSI Design.

Ultra Low Power Circuit Design Using Tunnel FETs

Narayanan Vijaykrishnan, Mary Jane Irwin, Vinay Saripalli, 2012, 2012 IEEE Computer Society Annual Symposium on VLSI.

The Third Eye: A Shopping Assistant for the Visually Impaired

Narayanan Vijaykrishnan, Mary Beth Rosson, John M. Carroll, 2017, CHI Extended Abstracts.

Power efficient adaptive M-QAM design using adaptive pipelined analog-to-digital converter

Narayanan Vijaykrishnan, Mary Jane Irwin, Rajarathnam Chandramouli, 2002, 2002 IEEE International Conference on Acoustics, Speech, and Signal Processing.

Energy-aware compilation and execution in Java-enabled mobile devices

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2003, Proceedings International Parallel and Distributed Processing Symposium.

Interconnect and thermal-aware floorplanning for 3D microprocessors

Narayanan Vijaykrishnan, Mary Jane Irwin, Yuan Xie, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

Using complete machine simulation for software power estimation: the SoftWatt approach

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2002, Proceedings Eighth International Symposium on High Performance Computer Architecture.

Influence of array allocation mechanisms on memory system energy

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2001, Proceedings 15th International Parallel and Distributed Processing Symposium. IPDPS 2001.

Hardware and Software Techniques for Controlling DRAM Power Modes

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2001, IEEE Trans. Computers.

Dynamic machine learning based matching of nonvolatile processor microarchitecture to harvested energy profile

Narayanan Vijaykrishnan, Yuan Xie, Xueqing Li, 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Impact of process scaling on the efficacy of leakage reduction schemes

Narayanan Vijaykrishnan, Mary Jane Irwin, D. Duarte, 2004, ICICDT 2004.

A clock power model to evaluate impact of architectural and technology optimizations

Narayanan Vijaykrishnan, Mary Jane Irwin, D. E. Duarte, 2002, IEEE Trans. Very Large Scale Integr. Syst..

Reliability-aware Co-synthesis for Embedded Systems

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2004, Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004..

Three-dimensional cache design exploration using 3DCacti

Narayanan Vijaykrishnan, Mary Jane Irwin, Yuan Xie, 2005, 2005 International Conference on Computer Design.

SUBGEN: a genetic approach for subcircuit extraction

Narayanan Vijaykrishnan, N. Ranganathan, 1996, Proceedings of 9th International Conference on VLSI Design.

Data Organization and Retrieval on Parallel Air Channels: Performance and Energy Issues

Narayanan Vijaykrishnan, Ali R. Hurson, Soontae Kim, 2004, Wirel. Networks.

Analyzing data reuse for cache reconfiguration

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2005, TECS.

Analysis of error recovery schemes for networks on chips

Luca Benini, Narayanan Vijaykrishnan, Mary Jane Irwin, 2005, IEEE Design & Test of Computers.

Editorial

Narayanan Vijaykrishnan, Charles J. Alpert, Sara Dailey, 2015, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Compiler-directed instruction cache leakage optimization

Wei Zhang, Narayanan Vijaykrishnan, Mary Jane Irwin, 2002, 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings..

Designing energy-efficient NoC for real-time embedded systems through slack optimization

Narayanan Vijaykrishnan, Lothar Thiele, Yuan Xie, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

IAA: Incidental Approximate Architectures for Extremely Energy-Constrained Energy Harvesting Scenarios using IoT Nonvolatile Processors

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Yuan Xie, 2018, IEEE Micro.

Working with Process Variation Aware Caches

Narayanan Vijaykrishnan, Madhu Mutyam, N. Vijaykrishnan, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

Reliability concerns in embedded system designs

Narayanan Vijaykrishnan, Yuan Xie, 2006, Computer.

Low-power high-speed current mode logic using Tunnel-FETs

Narayanan Vijaykrishnan, Xueqing Li, Huichu Liu, 2014, 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC).

A parallel architecture for hardware face detection

Narayanan Vijaykrishnan, Mary Jane Irwin, Theocharis Theocharides, 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

Emerging Reconfigurable Nanotechnologies: Can they support Future Electronics?

Narayanan Vijaykrishnan, Xiaobo Sharon Hu, Pierre-Emmanuel Gaillardon, 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Video analytics using beyond CMOS devices

Narayanan Vijaykrishnan, Gert Cauwenberghs, H.-S. Philip Wong, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

MDACache: Caching for Multi-Dimensional-Access Memories

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Jack Sampson, 2018, 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

A CLB architecture for Online correction of SEU-based Errors in LUTs of SRAM-based FPGAs

Narayanan Vijaykrishnan, V Kamakoti, Vikram Chandrasekhar, 2005 .

Symmetric encryption in reconfigurable and custom hardware

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2005, Int. J. Embed. Syst..

Introduction to Special Issue on Neuromorphic Computing

Narayanan Vijaykrishnan, Dan Hammerstrom, 2015, ACM J. Emerg. Technol. Comput. Syst..

Energy savings through compression in embedded Java environments

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2002, Proceedings of the Tenth International Symposium on Hardware/Software Codesign. CODES 2002 (IEEE Cat. No.02TH8627).

When to forget: A system-level perspective on STT-RAMs

Cong Xu, Narayanan Vijaykrishnan, Karthik Swaminathan, 2012, 17th Asia and South Pacific Design Automation Conference.

Three-Dimensional Network-on-Chip Architecture

Chita R. Das, Narayanan Vijaykrishnan, Yuan Xie, 2010 .

A Unified Energy Estimation Framework with Integrated Hardware-Software Optimizations

Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut Kandemir, 2000, ISCA 2000.

Detecting SEU-caused routing errors in SRAM-based FPGAs

V. Kamakoti, Narayanan Vijaykrishnan, Vikram Chandrasekhar, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

Transaction level error susceptibility model for bus based SoC architectures

Narayanan Vijaykrishnan, Nagu R. Dhanwada, Ing-Chao Lin, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

A reconfigurable accelerator for neuromorphic object recognition

Narayanan Vijaykrishnan, Deepak Khosla, Yang Chen, 2012, 17th Asia and South Pacific Design Automation Conference.

Interplay of energy and performance for disk arrays running transaction processing workloads

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2003, 2003 IEEE International Symposium on Performance Analysis of Systems and Software. ISPASS 2003..

Temperature-aware voltage islands architecting in system-on-chip design

Narayanan Vijaykrishnan, Yuan Xie, Nagu R. Dhanwada, 2005, 2005 International Conference on Computer Design.

Design considerations for databus charge recovery

Benjamin Bishop, Narayanan Vijaykrishnan, Mary Jane Irwin, 2001, IEEE Trans. Very Large Scale Integr. Syst..

Exploring Gabor Filter Implementations for Visual Cortex Modeling on FPGA

Narayanan Vijaykrishnan, Sungmin Bae, Kevin M. Irick, 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

Inverse discrete cosine transform architecture exploiting sparseness and symmetry properties

Narayanan Vijaykrishnan, Mary Jane Irwin, R. Radhakrishnan, 2004 .

A data-driven approach for embedded security

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Ozcan Ozturk, 2005, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05).

Saliency aware display power management

Narayanan Vijaykrishnan, Naehyuck Chang, Donghwa Shin, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Masking the Energy Behavior of DES Encryption

Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut Kandemir, 2003, DATE.

Accelerating the Nonuniform Fast Fourier Transform Using FPGAs

Narayanan Vijaykrishnan, Kevin M. Irick, Sungho Park, 2010, 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines.

A parallel architecture for secure FPGA symmetric encryption

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..

Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs

Chita R. Das, Narayanan Vijaykrishnan, Reetuparna Das, 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

Design Space Exploration for 3-D Cache

Narayanan Vijaykrishnan, Mary Jane Irwin, Yuan Xie, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Test Generation for Precise Interrupts on Out-of-Order Microprocessors

Narayanan Vijaykrishnan, David L. Landis, Padmaraj Singh, 2009, 2009 10th International Workshop on Microprocessor Test and Verification.

Predictive Precharging for Bitline Leakage Energy Reduction

Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut Kandemir, 2002 .

Priority Scheduling in Digital Microfluidics-Based Biochips

Narayanan Vijaykrishnan, Mary Jane Irwin, Kevin M. Irick, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Mitigating Thermal Effects on Clock Skew with Dynamically Adaptive Drivers

Narayanan Vijaykrishnan, Yehia Massoud, Greg M. Link, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs

V. Kamakoti, Narayanan Vijaykrishnan, Vikram Chandrasekhar, 2004, Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921).

The sandbox design experience course

Narayanan Vijaykrishnan, David L. Landis, Ivan S. Kourtev, 2003, Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03.

Using Multiple-Input NEMS for Parallel A/D Conversion and Image Processing

Narayanan Vijaykrishnan, Yuan Xie, Xueqing Li, 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.

Computation and transmission energy modeling through profiling for MPEG4 video transmission

Narayanan Vijaykrishnan, Mary Jane Irwin, Rajarathnam Chandramouli, 2003, 2003 International Conference on Multimedia and Expo. ICME '03. Proceedings (Cat. No.03TH8698).

Noise Aware Power Adaptive Partitioned Deep Networks for Mobile Visual Assist Platforms

Narayanan Vijaykrishnan, Jack Sampson, Peter A. Zientara, 2018, 2018 31st IEEE International System-on-Chip Conference (SOCC).

Leakage Optimized DECAP Design for FPGAs

Rong Luo, Narayanan Vijaykrishnan, Yuan Xie, 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support

Narayanan Vijaykrishnan, Meng-Fan Chang, Swaroop Ghosh, 2018, ISLPED.

New-Age: A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural Components

Yu Wang, Narayanan Vijaykrishnan, Yu Cao, 2009, International Journal of Parallel Programming.

Reducing instruction cache energy consumption using a compiler-based strategy

Wei Zhang, Mahmut T. Kandemir, Narayanan Vijaykrishnan, 2004, TACO.

Run-time adaption for highly-complex multi-core systems

Narayanan Vijaykrishnan, Jürgen Teich, Jörg Henkel, 2013, 2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

Security issues in embedded system design

Narayanan Vijaykrishnan, Mahmut Kandemir, Hendra Saputra, 2005 .

Design space exploration of workload-specific last-level caches

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Emre Kultursay, 2012, ISLPED '12.

Networks on Chip (NoC): Interconnects of Next Generation Systems on Chip

Narayanan Vijaykrishnan, Mary Jane Irwin, Theocharis Theocharides, 2005, Adv. Comput..

Compiler-directed thermal management for VLIW functional units

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2006, LCTES.

Power Analysis Attack Resistance Engineering by Dynamic Voltage and Frequency Scaling

Narayanan Vijaykrishnan, Yuan Xie, Marilyn Wolf, 2012, TECS.

Optimising power efficiency in trace cache fetch unit

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2007, IET Comput. Digit. Tech..

A framework for energy estimation of VLIW architecture

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.

Optimizing power and performance for reliable on-chip networks

Narayanan Vijaykrishnan, Mary Jane Irwin, Soumya Eachempati, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

Energy-efficient Java execution using local memory and object co-location

Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut Kandemir, 2004 .

Guest Editorial

Narayanan Vijaykrishnan, Christian Piguet, 2004, IEEE Trans. Very Large Scale Integr. Syst..

TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platform

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Chaitali Chakrabarti, 2007, 2007 International Conference on Field Programmable Logic and Applications.

MIRA: A Multi-layered On-Chip Interconnect Router Architecture

Chita R. Das, Narayanan Vijaykrishnan, Reetuparna Das, 2008, 2008 International Symposium on Computer Architecture.

System-On-Chip for Biologically Inspired Vision Applications

Narayanan Vijaykrishnan, Sungho Park, Ahmed Al-Maashri, 2012, IPSJ Trans. Syst. LSI Des. Methodol..

Compiler-directed instruction cache leakage optimization

Wei Zhang, Mahmut T. Kandemir, Narayanan Vijaykrishnan, 2002, MICRO.

Variation aware placement for FPGAs

Narayanan Vijaykrishnan, Suresh Srinivasan, 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

Tuning garbage collection for reducing memory system energy in an embedded java environment

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2002, TECS.

Non-volatile Logic and Memory based on Reconfigurable Ferroelectric Transistors

Narayanan Vijaykrishnan, Arnab Raha, Sumeet Kumar Gupta, 2019, 2019 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

Adaptive error protection for energy efficiency

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

Modeling steep slope devices: From circuits to architectures

Narayanan Vijaykrishnan, Robert Perricone, Behnam Sedighi, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Device Circuit Co Design of FEFET Based Logic for Low Voltage Processors

Narayanan Vijaykrishnan, Xueqing Li, Suman Datta, 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Data Organization and Retrieval on Parallel Air Channels

Narayanan Vijaykrishnan, Ali R. Hurson, J. Juran, 2000, HiPC.

Influence of compiler optimizations on system power

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2000, Proceedings 37th Design Automation Conference.

NEBULA: A Neuromorphic Spin-Based Ultra-Low Power Architecture for SNNs and ANNs

Chita R. Das, Narayanan Vijaykrishnan, Sen Lu, 2020, 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA).

Switch Box Architectures for Three-Dimensional FPGAs

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Arif Rahman, 2006, 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

Input sensitive high-level power analysis

Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut Kandemir, 2001, 2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578).

Exploring technology alternatives for nano-scale FPGA interconnects

Narayanan Vijaykrishnan, Mary Jane Irwin, Aman Gayasen, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Ultra Low Energy Binary Decision Diagram Circuits Using Few Electron Transistors

Narayanan Vijaykrishnan, Vinay Saripalli, Suman Datta, 2009, NanoNet.

Effect of compiler optimizations on memory energy

Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut Kandemir, 2000, 2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS 2000. Design and Implementation (Cat. No.00TH8528).

Indoor Navigation using Text Extraction

Narayanan Vijaykrishnan, Jake Eden, Thomas Kawchak, 2018, 2018 IEEE International Workshop on Signal Processing Systems (SiPS).

Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network

Narayanan Vijaykrishnan, Mary Jane Irwin, Yuan Xie, 2009, 2009 IEEE/ACM International Symposium on Nanoscale Architectures.

Exploring memory controller configurations for many-core systems with 3D stacked DRAMs

Narayanan Vijaykrishnan, Yuan Xie, Fen Ge, 2015, Sixteenth International Symposium on Quality Electronic Design.

A linear array processor with dynamic frequency clocking for image processing applications

Narayanan Vijaykrishnan, N. Ranganathan, N. Bhavanishankar, 1998, IEEE Trans. Circuits Syst. Video Technol..

On-chip Bus Thermal Analysis and Optimization

Narayanan Vijaykrishnan, Mary Jane Irwin, Yuan Xie, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Design and analysis of an NoC architecture from performance, reliability and energy perspective

Chita R. Das, Narayanan Vijaykrishnan, Jongman Kim, 2005, 2005 Symposium on Architectures for Networking and Communications Systems (ANCS).

Understanding and improving operating system effects in control flow prediction

Narayanan Vijaykrishnan, Anand Sivasubramaniam, Lizy Kurian John, 2002, ASPLOS X.

Saliency-driven dynamic configuration of HMAX for energy-efficient multi-object recognition

Narayanan Vijaykrishnan, Sungho Park, Ahmed Al-Maashri, 2013, 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

A Configurable Architecture for a Visual Saliency System and Its Application in Retail

Narayanan Vijaykrishnan, Nandhini Chandramoorthy, Kevin M. Irick, 2013, 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines.

Block-based frequency scalable technique for efficient hierarchical coding

Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, 2006, IEEE Transactions on Signal Processing.

Context-Aware Collaborative Object Recognition For Distributed Multi Camera Time Series Data

Narayanan Vijaykrishnan, Philip W. Shin, Jack Sampson, 2019, SoICT 2019.

Integrated CAM-RAM Functionality using Ferroelectric FETs

Narayanan Vijaykrishnan, Xueqing Li, Jack Sampson, 2020, 2020 21st International Symposium on Quality Electronic Design (ISQED).

Scheduler-based DRAM energy management

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2002, DAC '02.

The Third Eye: A Shopping Assistant for the Visually Impaired

Narayanan Vijaykrishnan, John M. Carroll, Sooyeon Lee, 2017, CHI Extended Abstracts.

Architectural issues in Java runtime systems

Narayanan Vijaykrishnan, Ramesh Radhakrishnan, Anand Sivasubramaniam, 2000, Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No.PR00550).

Object-Oriented Architectural Support for a Java Processor

Narayanan Vijaykrishnan, N. Ranganathan, Ravi Gadekarla, 1998, ECOOP.

Characterization and modeling of run-time techniques for leakage power reduction

Narayanan Vijaykrishnan, Mary Jane Irwin, Yuh-Fang Tsai, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Multiple access caches: Energy implications

Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut Kandemir, 2000, Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era.

Variation-Aware Task and Communication Mapping for MPSoC Architecture

Narayanan Vijaykrishnan, Xiaoxia Wu, Yuan Xie, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Using dynamic branch behavior for power-efficient instruction fetch

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2003, IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings..

Compiler-directed array interleaving for reducing energy in multi-bank memories

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

Performance and power optimization through data compression in Network-on-Chip architectures

Chita R. Das, Narayanan Vijaykrishnan, Reetuparna Das, 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.

Analyzing heap error behavior in embedded JVM environments

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2004, International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004..

Always-On Speech Recognition Using TrueNorth, a Reconfigurable, Neurosynaptic Processor

Narayanan Vijaykrishnan, Andrew S. Cassidy, Alexander Andreopoulos, 2017, IEEE Transactions on Computers.

SoC design skills: collaboration builds a stronger SoC design team

Narayanan Vijaykrishnan, Mary Jane Irwin, Steven P. Levitan, 2001, Proceedings 2001 International Conference on Microelectronic Systems Education.

Hardware Acceleration for Neuromorphic Vision Algorithms

Narayanan Vijaykrishnan, Chi-Li Yu, Ahmed Al-Maashri, 2013, J. Signal Process. Syst..

Impact of technology scaling in the clock system power

Narayanan Vijaykrishnan, Mary Jane Irwin, David Duarte, 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

Optimizing the NoC Slack Through Voltage and Frequency Scaling in Hard Real-Time Embedded Systems

Narayanan Vijaykrishnan, Lothar Thiele, Yuan Xie, 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Hardware-software co-adaptation for data-intensive embedded applications

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

A case for heterogeneous on-chip interconnects for CMPs

Chita R. Das, Narayanan Vijaykrishnan, Asit K. Mishra, 2011, 2011 38th Annual International Symposium on Computer Architecture (ISCA).

Adapting instruction level parallelism for optimizing leakage in VLIW architectures

Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut Kandemir, 2003 .

Design of Thermally Robust Clock Trees Using Dynamically Adaptive Clock Buffers

Narayanan Vijaykrishnan, Yehia Massoud, Greg M. Link, 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

Adaptive Garbage Collection for Battery-Operated Environments

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2002, Java Virtual Machine Research and Technology Symposium.

Implications of technology scaling on leakage reduction techniques

Narayanan Vijaykrishnan, Mary Jane Irwin, Yuh-Fang Tsai, 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

Exploration of Low-Power High-SFDR Current-Steering D/A Converter Design Using Steep-Slope Heterojunction Tunnel FETs

Narayanan Vijaykrishnan, Xueqing Li, Suman Datta, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A power estimation methodology for systemC transaction level models

Narayanan Vijaykrishnan, Nagu R. Dhanwada, Ing-Chao Lin, 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

A compiler-based approach for dynamically managing scratch-pad memories in embedded systems

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Architecting Microprocessor Components in 3D Design Space

Narayanan Vijaykrishnan, Mary Jane Irwin, Yuan Xie, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

Reliability-aware design for nanometer-scale devices

Luca Benini, Narayanan Vijaykrishnan, Giovanni De Micheli, 2008, 2008 Asia and South Pacific Design Automation Conference.

Monolithic-3D Integration Augmented Design Techniques for Computing in SRAMs

Narayanan Vijaykrishnan, Meng-Fan Chang, Jack Sampson, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

A scalable architecture for multi-class visual object detection

Narayanan Vijaykrishnan, Jack Sampson, Kevin M. Irick, 2015, 2015 25th International Conference on Field Programmable Logic and Applications (FPL).

Impact of Circuit Degradation on FPGA Design Security

Narayanan Vijaykrishnan, Yuan Xie, Han-Wei Chen, 2011, 2011 IEEE Computer Society Annual Symposium on VLSI.

Exploiting clock skew scheduling for FPGA

Narayanan Vijaykrishnan, Sungmin Bae, Prasanth Mangalagiri, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

Exploiting value locality for secure-energy aware communication

Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut Kandemir, 2003, 2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682).

TS-Router: On maximizing the Quality-of-Allocation in the On-Chip Network

Chung-Ta King, Narayanan Vijaykrishnan, Matthew Poremba, 2013, 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA).

Heap compression for memory-constrained Java environments

Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut Kandemir, 2003, OOPSLA 2003.

Total Power Optimization for Combinational Logic Using Genetic Algorithms

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2010, J. Signal Process. Syst..

A novel Si-Tunnel FET based SRAM design for ultra low-power 0.3V VDD applications

Dhiraj K. Pradhan, Narayanan Vijaykrishnan, Jawar Singh, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

Energy efficient datapath synthesis using dynamic frequency clocking and multiple voltages

Narayanan Vijaykrishnan, N. Ranganathan, Vamsi Krishna, 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

Emulating Mammalian Vision on Reconfigurable Hardware

Narayanan Vijaykrishnan, Deepak Khosla, Yang Chen, 2012, 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines.

Compiler-assisted soft error detection under performance and energy constraints in embedded systems

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2009, TECS.

Accelerating neuromorphic vision algorithms for recognition

Narayanan Vijaykrishnan, Ahmed Al-Maashri, Nandhini Chandramoorthy, 2012, DAC Design Automation Conference 2012.

Variation Impact on SER of Combinational Circuits

Narayanan Vijaykrishnan, Mary Jane Irwin, Yuan Xie, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

Evaluating run-time techniques for leakage power reduction

Narayanan Vijaykrishnan, Mary Jane Irwin, Yuh-Fang Tsai, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays

Narayanan Vijaykrishnan, Yuan Xie, Soumya Eachempati, 2013, JETC.

Analyzing Energy-Delay Behavior in Room Temperature Single Electron Transistors

Narayanan Vijaykrishnan, Vinay Saripalli, Suman Datta, 2010, 2010 23rd International Conference on VLSI Design.

Soft errors issues in low-power caches

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Exploiting program hotspots and code sequentiality for instruction cache leakage management

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2003, ISLPED '03.

A Novel Low Area Overhead Body Bias FPGA Architecture for Low Power Applications

Narayanan Vijaykrishnan, Sungmin Bae, Krishnan Ramakrishnan, 2009, 2009 IEEE Computer Society Annual Symposium on VLSI.

Thermal Gradient Aware Clock Skew Scheduling for FPGAs

Narayanan Vijaykrishnan, Sungmin Bae, N. Vijaykrishnan, 2010, 2010 International Conference on Field Programmable Logic and Applications.

Improving soft-error tolerance of FPGA configuration bits

Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut Kandemir, 2004, ICCAD 2004.

A Holistic Approach to System Level Energy Optimization

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2000, PATMOS.

Impact of Process Variations on Carbon Nanotube Bundle Interconnect for Future FPGA Architectures

Narayanan Vijaykrishnan, Soumya Eachempati, Arthur Nieuwoudt, 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).

Search speed and power driven integrated software and hardware optimizations for motion estimation algorithms

Narayanan Vijaykrishnan, Wayne H. Wolf, Shengqi Yang, 2004, 2004 IEEE International Conference on Multimedia and Expo (ICME) (IEEE Cat. No.04TH8763).

A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks

Chita R. Das, Narayanan Vijaykrishnan, Jongman Kim, 2006, 33rd International Symposium on Computer Architecture (ISCA'06).

Heap compression for memory-constrained Java environments

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2003, OOPSLA.

A novel dimensionally-decomposed router for on-chip communication in 3D architectures

Chita R. Das, Narayanan Vijaykrishnan, Reetuparna Das, 2007, ISCA '07.

Variation-aware task allocation and scheduling for MPSoC

Narayanan Vijaykrishnan, Chrysostomos Nicopoulos, Feng Wang, 2007, ICCAD 2007.

Studying energy trade offs in offloading computation/compilation in Java-enabled mobile devices

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2004, IEEE Transactions on Parallel and Distributed Systems.

Leveraging Emerging Technology Through Architectural Exploration for the Routing Fabric of Future FPGAs

Narayanan Vijaykrishnan, Mary Jane Irwin, Soumya Eachempati, 2011 .

Compiler-directed high-level energy estimation and optimization

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2005, TECS.

A Hardware Efficient Support Vector Machine Architecture for FPGA

Narayanan Vijaykrishnan, Aman Gayasen, Kevin M. Irick, 2008, 2008 16th International Symposium on Field-Programmable Custom Computing Machines.

Energy-oriented compiler optimizations for partitioned memory architectures

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2000, CASES '00.

Introduction to the Special Issue on Domain-Specific Multicore Computing

Narayanan Vijaykrishnan, Jürgen Teich, 2014, ACM Trans. Embed. Comput. Syst..

Efficient VLSI implementation of inverse discrete cosine transform [image coding applications]

Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, 2004, 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing.

The effect of threshold voltages on the soft error rate [memory and logic circuits]

Narayanan Vijaykrishnan, Mary Jane Irwin, Yuan Xie, 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).

Platform-aware dynamic configuration support for efficient text processing on heterogeneous system

Narayanan Vijaykrishnan, Mary Jane Irwin, Ravi Iyer, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Intelligent Vision Systems: Exploring the State-of-the-Art and Opportunities for the Future

Narayanan Vijaykrishnan, Siddharth Advani, Srinidhi Kestur, 2015, 2015 IEEE International Symposium on Nanoelectronic and Information Systems.

Power-efficient trace caches

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

Instruction scheduling based on energy and performance constraints

Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut Kandemir, 2000, Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era.

Simultaneous partitioning and frequency assignment for on-chip bus architectures

Narayanan Vijaykrishnan, Suresh Srinivasan, Lin Li, 2005, Design, Automation and Test in Europe.

Morphable Cache Architectures: Potential Benefits

Narayanan Vijaykrishnan, Mary Jane Irwin, Ismail Kadayif, 2001 .

Investigating Memory System Energy Behavior Using Software and Hardware Optimizations

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2001, VLSI Design.

Editorial

Narayanan Vijaykrishnan, Charles J. Alpert, Sara Dailey, 2016, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Spendthrift: Machine learning based resource and frequency scaling for ambient energy harvesting nonvolatile processors

Narayanan Vijaykrishnan, Yuan Xie, Xueqing Li, 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

Power attack resistant cryptosystem design: a dynamic voltage and frequency switching approach

Narayanan Vijaykrishnan, Yuan Xie, Wayne H. Wolf, 2005, Design, Automation and Test in Europe.

Power-efficient implementation of turbo decoder in SDR system

Narayanan Vijaykrishnan, Mary Jane Irwin, Theocharis Theocharides, 2004, IEEE International SOC Conference, 2004. Proceedings..

Architecture exploration for ambient energy harvesting nonvolatile processors

Narayanan Vijaykrishnan, Yuan Xie, Yang Zheng, 2015, 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA).

Using Memory Compression for Energy Reduction in an Embedded Java System

Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut Kandemir, 2002, J. Circuits Syst. Comput..

Improving Java performance using dynamic method migration on FPGAs

Luca Benini, Mahmut T. Kandemir, Narayanan Vijaykrishnan, 2005, Int. J. Embed. Syst..

Energy-driven integrated hardware-software optimizations using SimplePower

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

Exploring Wakeup-Free Instruction Scheduling

Narayanan Vijaykrishnan, Mary Jane Irwin, Jie S. Hu, 2004, 10th International Symposium on High Performance Computer Architecture (HPCA'04).

Compiler-directed instruction duplication for soft error detection

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2005, Design, Automation and Test in Europe.

Use of local memory for efficient Java execution

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.

Co-training of feature extraction and classification using partitioned convolutional neural networks

Chita R. Das, Narayanan Vijaykrishnan, Jinhang Choi, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

Impact of scaling on the effectiveness of dynamic power reduction schemes

Narayanan Vijaykrishnan, Mary Jane Irwin, Hyun Suk Kim, 2002, Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Mitigating electromigration of power supply networks using bidirectional current stress

Narayanan Vijaykrishnan, Yuan Xie, Jing Xie, 2012, GLSVLSI '12.

Invited paper: Accelerating neuromorphic vision on FPGAs

Narayanan Vijaykrishnan, Kevin M. Irick, Sungho Park, 2011, CVPR 2011 WORKSHOPS.

Exploring Fault-Tolerant Network-on-Chip Architectures

Chita R. Das, Narayanan Vijaykrishnan, Jongman Kim, 2006, International Conference on Dependable Systems and Networks (DSN'06).

Energy-Delay Performance of Nanoscale Transistors Exhibiting Single Electron Behavior and Associated Logic Circuits

Narayanan Vijaykrishnan, Lu Liu, Vinay Saripalli, 2010, J. Low Power Electron..

Computational Architectures Based on Coupled Oscillators

Narayanan Vijaykrishnan, Donald M. Chiarulli, Steven P. Levitan, 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

Reducing dTLB energy through dynamic resizing

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2003, Proceedings 21st International Conference on Computer Design.

A nanosensor array-based VLSI gas discriminator

Narayanan Vijaykrishnan, Mary Jane Irwin, Wei Xu, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

Energy-Aware Instruction Scheduling

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2000, HiPC.

Reliability-aware SOC voltage islands partition and floorplan

Narayanan Vijaykrishnan, Yuan Xie, Wayne H. Wolf, 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

Comparative analysis of NBTI effects on low power and high performance flip-flops

Narayanan Vijaykrishnan, Xiaoxia Wu, Yuan Xie, 2008, 2008 IEEE International Conference on Computer Design.

Hierarchical Soft Error Estimation Tool (HSEET)

Narayanan Vijaykrishnan, Mary Jane Irwin, Yuan Xie, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

Soft errors: is the concern for soft-errors overblown?

Narayanan Vijaykrishnan, 2005, IEEE International Conference on Test, 2005..

Enabling architectural innovations using non-volatile memory

Narayanan Vijaykrishnan, Yuan Xie, Vinay Saripalli, 2011, GLSVLSI '11.

Nonvolatile Processor Architecture Exploration for Energy-Harvesting Applications

Narayanan Vijaykrishnan, Yuan Xie, Xueqing Li, 2015, IEEE Micro.

Steep switching tunnel FET: A promise to extend the energy efficient roadmap for post-CMOS digital and analog/RF applications

Narayanan Vijaykrishnan, Suman Datta, Huichu Liu, 2013, International Symposium on Low Power Electronics and Design (ISLPED).

Refresh Enabled Video Analytics (REVA): Implications on power and performance of DRAM supported embedded visual systems

Narayanan Vijaykrishnan, Jack Sampson, Nandhini Chandramoorthy, 2014, 2014 IEEE 32nd International Conference on Computer Design (ICCD).

Leakage control in FPGA routing fabric

Narayanan Vijaykrishnan, Tim Tuan, Aman Gayasen, 2005, ASP-DAC.

FLAW: FPGA lifetime awareness

Narayanan Vijaykrishnan, Yuan Xie, Prasanth Mangalagiri, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs

Chita R. Das, Narayanan Vijaykrishnan, Yuan Xie, 2011, 2011 38th Annual International Symposium on Computer Architecture (ISCA).

Hazard driven test generation for SMT processors

Narayanan Vijaykrishnan, David L. Landis, Padmaraj Singh, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Exploiting VLIW schedule slacks for dynamic and leakage energy reduction

Wei Zhang, Narayanan Vijaykrishnan, Mary Jane Irwin, 2001, Proceedings. 34th ACM/IEEE International Symposium on Microarchitecture. MICRO-34.

Security and Dependability of Embedded Systems: A Computer Architects' Perspective

Narayanan Vijaykrishnan, Sri Parameswaran, Roshan G. Ragel, 2009, VLSI Design.

Tuning Branch Predictors to Support Virtual Method Invocation in Java

Narayanan Vijaykrishnan, N. Ranganathan, 1999, COOTS.

Managing Leakage Energy in Cache Hierarchies

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2003, J. Instr. Level Parallelism.

Look-Up Table based Energy Efficient Processing in Cache Support for Neural Network Acceleration

Narayanan Vijaykrishnan, Sreenivas Subramoney, Om Ji Omer, 2020, 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits

Narayanan Vijaykrishnan, Mary Jane Irwin, Yuan Xie, 2009, IEEE Transactions on Dependable and Secure Computing.

Independently-Controlled-Gate FinFET 6T SRAM Cell Design for Leakage Current Reduction and Enhanced Read Access Speed

Narayanan Vijaykrishnan, Yuan Xie, Yang Zheng, 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

Energy-performance trade-offs for spatial access methods on memory-resident data

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2002, The VLDB Journal.

Analyzing software influences on substrate noise: an ADC perspective

Narayanan Vijaykrishnan, Mary Jane Irwin, Frank Ghenassia, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

Energy-efficient instruction cache using page-based placement

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2001, CASES '01.

Evaluation of tunnel FET-based flip-flop designs for low power, high performance applications

Narayanan Vijaykrishnan, Suman Datta, Huichu Liu, 2013, International Symposium on Quality Electronic Design (ISQED).

A comparative study of power efficient SRAM designs

Narayanan Vijaykrishnan, Mary Jane Irwin, M. J. Irwin, 2000, ACM Great Lakes Symposium on VLSI.

Guest Editorial Advances in Design of Energy-Efficient Circuits and Systems (Second Issue)

Narayanan Vijaykrishnan, Kaushik Roy, Enrico Macii, 2011, IEEE J. Emerg. Sel. Topics Circuits Syst..

Dynamic management of scratch-pad memory space

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

Instruction Scheduling for Low Power

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2004, J. VLSI Signal Process..

A low latency router supporting adaptivity for on-chip interconnects

Chita R. Das, Narayanan Vijaykrishnan, Jongman Kim, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Experimental Evaluation of Energy Behavior of Iteration Space Tiling

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2000, LCPC.

Partitioned instruction cache architecture for energy efficiency

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2003, TECS.

Steep slope devices: Enabling new architectural paradigms

Narayanan Vijaykrishnan, Xueqing Li, Huichu Liu, 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

Targeted random test generation for power-aware multicore designs

Narayanan Vijaykrishnan, David L. Landis, Padmaraj Singh, 2012, TODE.

Delay and energy efficient data transmission for on-chip buses

Narayanan Vijaykrishnan, Yuan Xie, Melvin Eze, 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

Tunnel FET-based ultra-low power, low-noise amplifier design for bio-signal acquisition

Narayanan Vijaykrishnan, Mahsa Shoaran, Alexandre Schmid, 2014, 2014 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

A Power-Efficient Hybrid Architecture Design for Image Recognition Using CNNs

Narayanan Vijaykrishnan, Jinhang Choi, Jack Sampson, 2018, 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

FPGA routing architecture analysis under variations

Narayanan Vijaykrishnan, Yuan Xie, Prasanth Mangalagiri, 2007, 2007 25th International Conference on Computer Design.

Design of energy-efficient circuits and systems using tunnel field effect transistors

Narayanan Vijaykrishnan, Mary Jane Irwin, Vinay Saripalli, 2013, IET Circuits Devices Syst..

An integer linear programming-based tool for wireless sensor networks

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2005, J. Parallel Distributed Comput..

Impact of NBTI on FPGAs

Narayanan Vijaykrishnan, Mary Jane Irwin, Krishnan Ramakrishnan, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

On reconfigurable Single-Electron Transistor arrays synthesis using reordering techniques

Narayanan Vijaykrishnan, Suman Datta, Yung-Chih Chen, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

NEOFog: Nonvolatility-Exploiting Optimizations for Fog Computing

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Yuan Xie, 2018, ASPLOS.

In-Network Caching for Chip Multiprocessors

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2009, HiPEAC.

Exploiting temporal loads for low latency and high bandwidth memory

Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut Kandemir, 2005 .

Thermal-aware IP virtualization and placement for networks-on-chip architecture

Narayanan Vijaykrishnan, Mary Jane Irwin, Yuan Xie, 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays

Narayanan Vijaykrishnan, Suman Datta, Yung-Chih Chen, 2015, The 20th Asia and South Pacific Design Automation Conference.

A High-Efficiency Switched-Capacitance HTFET Charge Pump for Low-Input-Voltage Applications

Narayanan Vijaykrishnan, Xueqing Li, Suman Datta, 2015, 2015 28th International Conference on VLSI Design.

EAC: a compiler framework for high-level energy estimation and optimization

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

An architecture for motion estimation in the transform domain

Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, 2004, 17th International Conference on VLSI Design. Proceedings..

A Scalable Bandwidth Aware Architecture for Connected Component Labeling

Narayanan Vijaykrishnan, Ahmed Al-Maashri, Kevin M. Irick, 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

Energy-conscious compilation based on voltage scaling

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2002, LCTES/SCOPES '02.

Performance Improvements through Timing Driven Reconfiguration of Black-Boxes in Platform FPGAs

Narayanan Vijaykrishnan, Kamal Chaudhary, Sridhar Krishnamurthy, 2006, 2006 IEEE International SOC Conference.

Clock power issues in system-on-a-chip designs

Narayanan Vijaykrishnan, Mary Jane Irwin, R. Y. Chen, 1999, Proceedings. IEEE Computer Society Workshop on VLSI '99. System Design: Towards System-on-a-Chip Paradigm.

Guest Editorial

Narayanan Vijaykrishnan, Christian Piguet, 2004, IEEE Trans. Very Large Scale Integr. Syst..

Estimating influence of data layout optimizations on SDRAM energy consumption

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2003, ISLPED '03.

Implementing LDPC decoding on network-on-chip

Narayanan Vijaykrishnan, Mary Jane Irwin, Theocharis Theocharides, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

Editorial

Narayanan Vijaykrishnan, 2017, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Thermally Robust Clocking Schemes for 3D Integrated Circuits

Narayanan Vijaykrishnan, Yehia Massoud, Greg M. Link, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

AutoFLEX: A Framework for Image Processing Applications on Multiple-FPGA Systems

Narayanan Vijaykrishnan, Sungho Park, Ahmed Al-Maashri, 2010, ERSA.

Tuning garbage collection in an embedded Java environment

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2002, Proceedings Eighth International Symposium on High Performance Computer Architecture.

Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays

Narayanan Vijaykrishnan, Suman Datta, Yung-Chih Chen, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

ResiRCA: A Resilient Energy Harvesting ReRAM Crossbar-Based Accelerator for Intelligent Embedded Processors

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Keni Qiu, 2020, 2020 IEEE International Symposium on High Performance Computer Architecture (HPCA).

Predictive precharging for bitline leakage energy reduction [microprocessor caches]

Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut Kandemir, 2002, 15th Annual IEEE International ASIC/SOC Conference.

A Saliency-Driven LCD Power Management System

Narayanan Vijaykrishnan, Naehyuck Chang, Donghwa Shin, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Tools and Techniques for Integrated Hardware-Software Energy Optimizations

Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam, 2002 .

IMC-Sort: In-Memory Parallel Sorting Architecture using Hybrid Memory Cube

Narayanan Vijaykrishnan, Nagadastagiri Challapalle, Akshay Krishna Ramanathan, 2020, ACM Great Lakes Symposium on VLSI.

Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only)

V. Kamakoti, Narayanan Vijaykrishnan, Vikram Chandrasekhar, 2005, FPGA '05.

Synthesis for Width Minimization in the Single-Electron Transistor Array

Narayanan Vijaykrishnan, Suman Datta, Yung-Chih Chen, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An FPGA-based accelerator for cortical object classification

Narayanan Vijaykrishnan, Mary Jane Irwin, Jagdish Sabarad, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

ShieldUS: A novel design of dynamic shielding for eliminating 3D TSV crosstalk coupling noise

Chung-Ta King, Narayanan Vijaykrishnan, Yuan-Ying Chang, 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

Fault tolerant algorithms for network-on-chip interconnect

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2004, IEEE Computer Society Annual Symposium on VLSI.

Visual co-occurrence network: using context for large-scale object recognition in retail

Narayanan Vijaykrishnan, Jack Sampson, Kevin M. Irick, 2015, 2015 13th IEEE Symposium on Embedded Systems For Real-time Multimedia (ESTIMedia).

A reconfigurable platform for the design and verification of domain-specific accelerators

Narayanan Vijaykrishnan, Kevin M. Irick, Sungho Park, 2012, 17th Asia and South Pacific Design Automation Conference.

Memory system energy (poster session): influence of hardware-software optimizations

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2000, ISLPED '00.

Clone Detection in Sensor Networks with Ad Hoc and Grid Topologies

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Richard R. Brooks, 2009, Int. J. Distributed Sens. Networks.

Accelerating Multiresolution Gabor Feature Extraction for Real Time Vision Applications

Narayanan Vijaykrishnan, Nandhini Chandramoorthy, Kevin M. Irick, 2014, J. Signal Process. Syst..

Cognitive cameras: Assistive vision systems

Narayanan Vijaykrishnan, Jack Sampson, Kevin M. Irick, 2015, 2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES).

AIGuide: An Augmented Reality Hand Guidance Application for People with Visual Impairments

Narayanan Vijaykrishnan, Mary Beth Rosson, John M. Carroll, 2020, ASSETS.

Characterizing dynamic and leakage power behavior in flip-flops

Narayanan Vijaykrishnan, Mary Jane Irwin, R. Ramanarayanan, 2002, 15th Annual IEEE International ASIC/SOC Conference.

Designing reliable circuit in the presence of soft errors

Narayanan Vijaykrishnan, Mary Jane Irwin, Yuan Xie, 2005, ASP-DAC.

Heuristic Approximation of Early-Stage CNN Data Representation for Vision Intelligence Systems

Narayanan Vijaykrishnan, Jinhang Choi, Jack Sampson, 2018, 2018 IEEE 36th International Conference on Computer Design (ICCD).

Editorial

Narayanan Vijaykrishnan, 2014, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Energy-aware code cache management for memory-constrained Java devices

Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut Kandemir, 2003, IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings..

Designing energy-efficient software

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2002, Proceedings 16th International Parallel and Distributed Processing Symposium.

Assessing Carbon Nanotube Bundle Interconnect for Future FPGA Architectures

Narayanan Vijaykrishnan, Soumya Eachempati, Arthur Nieuwoudt, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

Tracking object life cycle for leakage energy optimization

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).

Leakage Current: Moore's Law Meets Static Power

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2003, Computer.

Geometric Tiling for Reducing Power Consumption in Structured Matrix Operations

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Chaitali Chakrabarti, 2006, 2006 IEEE International SOC Conference.

A task-oriented vision system

Narayanan Vijaykrishnan, Yang Xiao, Jack Sampson, 2014, GLSVLSI '14.

A framework for accelerating neuromorphic-vision algorithms on FPGAs

Narayanan Vijaykrishnan, Chi-Li Yu, Ahmed Al-Maashri, 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Thermal-aware floorplanning using genetic algorithms

Narayanan Vijaykrishnan, Mary Jane Irwin, Yuan Xie, 2005, Sixth international symposium on quality electronic design (isqed'05).

Nonvolatile memory design based on ferroelectric FETs

Narayanan Vijaykrishnan, Meng-Fan Chang, Xueqing Li, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Hierarchical Soft Error Estimation Tool (HSEET)

Narayanan Vijaykrishnan, Mary Jane Irwin, Kenan Unlu, 2008, ISQED 2008.

Efficient image reconstruction using partial 2D Fourier transform

Narayanan Vijaykrishnan, Chaitali Chakrabarti, Chi-Li Yu, 2008, 2008 IEEE Workshop on Signal Processing Systems.

A complete phase-locked loop power consumption model

Narayanan Vijaykrishnan, Mary Jane Irwin, David Duarte, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

Investigating Simple Low Latency Reliable Multiported Register Files

Narayanan Vijaykrishnan, Mary Jane Irwin, Madhu Mutyam, 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).

VL-CDRAM: variable line sized cached DRAMs

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).

Thermal-aware task allocation and scheduling for embedded systems

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2005, Design, Automation and Test in Europe.

Stochastic Functional Verification of DNN Design through Progressive Virtual Dataset Generation

Narayanan Vijaykrishnan, Alan L. Yuille, Weichao Qiu, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

A multi-resolution saliency framework to drive foveation

Narayanan Vijaykrishnan, Kevin M. Irick, Siddharth Advani, 2013, 2013 IEEE International Conference on Acoustics, Speech and Signal Processing.

Analysis of soft error rate in flip-flops and scannable latches

Narayanan Vijaykrishnan, Mary Jane Irwin, D. Duarte, 2003, IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings..

DFLAP: a dynamic frequency linear array processor

Narayanan Vijaykrishnan, N. Ranganathan, N. Bhavanishankar, 1996, Proceedings of 3rd IEEE International Conference on Image Processing.

Compiler-directed cache polymorphism

Wei Zhang, Mahmut T. Kandemir, Narayanan Vijaykrishnan, 2002, LCTES/SCOPES '02.

A framework for estimating NBTI degradation of microarchitectural components

Yu Wang, Narayanan Vijaykrishnan, Yu Cao, 2009, 2009 Asia and South Pacific Design Automation Conference.

Impact of dynamic voltage and frequency scaling on the architectural vulnerability of GALS architectures

Narayanan Vijaykrishnan, Anand Sivasubramaniam, Niranjan Soundararajan, 2008, Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08).

Adapting instruction level parallelism for optimizing leakage in VLIW architectures

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2003, LCTES.

Automated mapping for reconfigurable single-electron transistor arrays

Narayanan Vijaykrishnan, Yuan Xie, Soumya Eachempati, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

An Accuracy Tunable Non-Boolean Co-Processor Using Coupled Nano-Oscillators

V. Kamakoti, Narayanan Vijaykrishnan, Xueqing Li, 2017, ACM J. Emerg. Technol. Comput. Syst..

Single-Ended and Differential MRAMs Based on Spin Hall Effect: A Layout-Aware Design Perspective

Narayanan Vijaykrishnan, Suman Datta, Moon Seok Kim, 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.

Keynote talk: Embedded vision systems

Narayanan Vijaykrishnan, 2013, VLSI Design.

Designing a 3-D FPGA: Switch Box Architecture and Thermal Issues

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Aman Gayasen, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Programmable Non-Volatile Memory Design Featuring Reconfigurable In-Memory Operations

Narayanan Vijaykrishnan, Jack Sampson, Abhronil Sengupta, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

Drones as collaborative sensors for image recognition

Narayanan Vijaykrishnan, Jinhang Choi, Jack Sampson, 2018, 2018 IEEE International Conference on Consumer Electronics (ICCE).

Influence of Stacked 3D Memory/Cache Architectures on GPUs

Narayanan Vijaykrishnan, Yuan Xie, Guangyu Sun, 2011, 3D Integration for NoC-based SoC Architectures.

Design of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects

Chita R. Das, Narayanan Vijaykrishnan, Reetuparna Das, 2007 .

Analyzing soft errors in leakage optimized SRAM design

Narayanan Vijaykrishnan, Mary Jane Irwin, Vijay Degalahal, 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

DRAM energy management using software and hardware directed power mode control

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2001, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture.

Efficient Function Evaluations with Lookup Tables for Structured Matrix Operations

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Chaitali Chakrabarti, 2007, 2007 IEEE Workshop on Signal Processing Systems.

An examination of the architecture and system-level tradeoffs of employing steep slope devices in 3D CMPs

Narayanan Vijaykrishnan, Huichu Liu, Jack Sampson, 2014, 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA).

An efficient architecture for motion estimation and compensation in the transform domain

Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, 2006, IEEE Transactions on Circuits and Systems for Video Technology.

Evaluating Integrated Hardware-Software Optimizations Using a Unified Energy Estimation Framework

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2003, IEEE Trans. Computers.

Software power optimisation

Narayanan Vijaykrishnan, Mahmut Kandemir, Guilin Chen, 2006 .

Green transistors to green architectures

Narayanan Vijaykrishnan, Suman Datta, 2009, ISLPED.

Reducing non-deterministic loads in low-power caches via early cache set resolution

Narayanan Vijaykrishnan, Mary Jane Irwin, Soontae Kim, 2007, Microprocess. Microsystems.

An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Chaitali Chakrabarti, 2009, IEEE Transactions on Computers.

A crosstalk aware interconnect with variable cycle transmission

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Lifetime Reliability Aware Design Flow Techniques for Dual-Vdd Based Platform FPGAs

Narayanan Vijaykrishnan, Prasanth Mangalagiri, 2009, 2009 IEEE Computer Society Annual Symposium on VLSI.

Reliability-Aware Co-Synthesis for Embedded Systems

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2004, ASAP.

Cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs

Chita R. Das, Cong Xu, Narayanan Vijaykrishnan, 2012, DAC Design Automation Conference 2012.

An efficient implementation of hierarchical image coding

Narayanan Vijaykrishnan, Mary Jane Irwin, J. Lee, 2003, 2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682).

A low-power phase change memory based hybrid cache architecture

Narayanan Vijaykrishnan, Mary Jane Irwin, Yuan Xie, 2008, GLSVLSI '08.

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006

Narayanan Vijaykrishnan, Yehea Ismail, Gang Qu, 2006, ACM Great Lakes Symposium on VLSI.

Multiresolution Gabor Feature Extraction for Real Time Applications

Narayanan Vijaykrishnan, Nandhini Chandramoorthy, Kevin M. Irick, 2012, 2012 IEEE Workshop on Signal Processing Systems.

Predicting the performance and reliability of future field programmable gate arrays routing architectures with carbon nanotube bundle interconnect

Narayanan Vijaykrishnan, Soumya Eachempati, Arthur Nieuwoudt, 2009, IET Circuits Devices Syst..

Java Runtime Systems: Characterization and Architectural Implications

Narayanan Vijaykrishnan, Ramesh Radhakrishnan, Anand Sivasubramaniam, 2001, IEEE Trans. Computers.

Towards Resilient Micro-architectures: Datapath Reliability Enhancement Using STT-MRAM

Narayanan Vijaykrishnan, Niranjan Soundararajan, Karthik Swaminathan, 2011, 2011 IEEE Computer Society Annual Symposium on VLSI.

Bandwidth-intensive FPGA architecture for multi-dimensional DFT

Narayanan Vijaykrishnan, Chaitali Chakrabarti, Chi-Li Yu, 2010, 2010 IEEE International Conference on Acoustics, Speech and Signal Processing.

Performance enhancement under power constraints using heterogeneous CMOS-TFET multicores

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Emre Kultursay, 2012, CODES+ISSS '12.

Analyzing energy behavior of spatial access methods for memory-resident data

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2001, VLDB.

An algorithm-architecture co-design framework for gridding reconstruction using FPGAs

Narayanan Vijaykrishnan, Sungho Park, Ahmed Al-Maashri, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

Improving FPGA Design with Monolithic 3D Integration Using High Dense Inter-Stack Via

Narayanan Vijaykrishnan, Meng-Fan Chang, Xueqing Li, 2017, 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Code protection for resource-constrained embedded devices

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2004, LCTES '04.

Towards a unified multiresolution vision model for autonomous ground robots

Narayanan Vijaykrishnan, Siddharth Advani, Bradley P. Wyble, 2016, Robotics Auton. Syst..

A unified energy framework with integrated hardware-software optimizations

Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut Kandemir, 2000, International Symposium on Computer Architecture.

A hardware accelerated multilevel visual classifier for embedded visual-assist systems

Narayanan Vijaykrishnan, Jack Sampson, Kevin M. Irick, 2014, 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Investigating the impact of NBTI on different power saving cache strategies

Dhiraj K. Pradhan, Narayanan Vijaykrishnan, Jawar Singh, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

DoubtNet: Using Semantic Context to Enable Adaptive Inference for the IoT

Narayanan Vijaykrishnan, Chonghan Lee, Jack Sampson, 2020, 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Ferroelectric Transistor based Non-Volatile Flip-Flop

Narayanan Vijaykrishnan, Suman Datta, Sumeet Kumar Gupta, 2016, ISLPED.

A Low-Voltage Low-Power LC Oscillator Using the Diode-Connected SymFET

Narayanan Vijaykrishnan, Xueqing Li, Suman Datta, 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

Optimizing Leakage Energy Consumption in Cache Bitlines

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2004, Des. Autom. Embed. Syst..

Field level analysis for heap space optimization in embedded java environments

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2004, ISMM '04.

Design of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects

Chita R. Das, Narayanan Vijaykrishnan, Reetuparna Das, 2007, 15th Annual IEEE Symposium on High-Performance Interconnects (HOTI 2007).

ChipPower: an architecture-level leakage simulator

Narayanan Vijaykrishnan, Mary Jane Irwin, Theocharis Theocharides, 2004, IEEE International SOC Conference, 2004. Proceedings..

Enabling Internet-of-Things: Opportunities brought by emerging devices, circuits, and architectures

Narayanan Vijaykrishnan, Xueqing Li, Kaisheng Ma, 2016, VLSI-SoC.

Thermal characterization and optimization in platform FPGAs

Narayanan Vijaykrishnan, Tim Tuan, Aman Gayasen, 2006, ICCAD.

FPGA architecture for 2D Discrete Fourier Transform based on 2D decomposition for large-sized data

Narayanan Vijaykrishnan, Chaitali Chakrabarti, Chi-Li Yu, 2009, SiPS.

Enabling New Computation Paradigms with HyperFET - An Emerging Device

Narayanan Vijaykrishnan, Donald M. Chiarulli, Steven P. Levitan, 2016, IEEE Transactions on Multi-Scale Computing Systems.

Width minimization in the Single-Electron Transistor array synthesis

Narayanan Vijaykrishnan, Suman Datta, Yung-Chih Chen, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Energy Efficient and Reliable System Design

Narayanan Vijaykrishnan, 2003, VLSI-SOC.

Leakage-aware interconnect for on-chip network

Narayanan Vijaykrishnan, Mary Jane Irwin, Yuan Xie, 2005, Design, Automation and Test in Europe.

Reducing Energy Consumption in Chip Multiprocessors Using Workload Variations

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2004, Ultra Low-Power Electronics and Design.

An FPGA Implementation of Information Theoretic Visual-Saliency System and Its Optimization

Narayanan Vijaykrishnan, Sungmin Bae, Kevin M. Irick, 2011, 2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines.

The Sleep Deprivation Attack in Sensor Networks: Analysis and Methods of Defense

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Sencun Zhu, 2006, Int. J. Distributed Sens. Networks.

A case for dynamic frequency tuning in on-chip networks

Chita R. Das, Narayanan Vijaykrishnan, Reetuparna Das, 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

Steep-Slope Devices: From Dark to Dim Silicon

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Emre Kultursay, 2013, IEEE Micro.

Variation Analysis of CAM Cells

Narayanan Vijaykrishnan, Mary Jane Irwin, Yuan Xie, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

Enabling Internet-of-Things: Opportunities brought by emerging devices, circuits, and architectures

Narayanan Vijaykrishnan, Xueqing Li, Kaisheng Ma, 2016, 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

Influence of compiler optimizations on system power

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2001, IEEE Trans. Very Large Scale Integr. Syst..

On the Detection of Clones in Sensor Networks Using Random Key Predistribution

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Richard R. Brooks, 2007, IEEE Transactions on Systems, Man, and Cybernetics, Part C (Applications and Reviews).

SEAT-LA: a soft error analysis tool for combinational logic

Narayanan Vijaykrishnan, Mary Jane Irwin, Yuan Xie, 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

Dynamic bandwidth adaptation using recognition accuracy prediction through pre-classification for embedded vision systems

Narayanan Vijaykrishnan, Yang Xiao, Chuanjun Zhang, 2013, 2013 IEEE 31st International Conference on Computer Design (ICCD).

A dynamic frequency linear array processor for image processing

Narayanan Vijaykrishnan, N. Ranganathan, N. Bhavanishankar, 1996, Proceedings of 13th International Conference on Pattern Recognition.

A Dual-VDD Low Power FPGA Architecture

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2004, FPL.

Improving soft-error tolerance of FPGA configuration bits

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

FARM: A Flexible Accelerator for Recurrent and Memory Augmented Neural Networks

Narayanan Vijaykrishnan, Jack Sampson, Nicholas Jao, 2020, Journal of Signal Processing Systems.

Toward Increasing FPGA Lifetime

Narayanan Vijaykrishnan, Mary Jane Irwin, Yuan Xie, 2008, IEEE Transactions on Dependable and Secure Computing.

Harnessing Emerging Technology for Compute-in-Memory Support

Narayanan Vijaykrishnan, Jack Sampson, Sumitha George, 2018, 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

VLIW scheduling for energy and performance

Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut Kandemir, 2001, Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems.

Editorial

Narayanan Vijaykrishnan, Mary Jane Irwin, 2005, JETC.

A novel low power CAM design

Narayanan Vijaykrishnan, Mary Jane Irwin, G. Thirugnanam, 2001, Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558).

Design and Management of 3D Chip Multiprocessors Using Network-in-Memory

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Yuan Xie, 2006, 33rd International Symposium on Computer Architecture (ISCA'06).

vEC: virtual energy counters

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2001, PASTE '01.

Exploiting natural redundancy in visual information

Narayanan Vijaykrishnan, Jack Sampson, Kevin M. Irick, 2014, 2014 IEEE 32nd International Conference on Computer Design (ICCD).

Masking the energy behavior of DES encryption [smart cards]

Wei Zhang, Mahmut T. Kandemir, Narayanan Vijaykrishnan, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Case Study of Reliability-Aware and Low-Power Design

Narayanan Vijaykrishnan, Yuan Xie, Wenping Wang, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Memory energy characterization and optimization for the SPEC2000 benchmarks

Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam, 2001 .

A hardware architecture for accelerating neuromorphic vision algorithms

Narayanan Vijaykrishnan, Chi-Li Yu, Ahmed Al-Maashri, 2011, 2011 IEEE Workshop on Signal Processing Systems (SiPS).

A generic reconfigurable neural network architecture as a network on chip

Narayanan Vijaykrishnan, Mary Jane Irwin, Theocharis Theocharides, 2004, IEEE International SOC Conference, 2004. Proceedings..

Nonvolatile processors: Why is it trending?

Narayanan Vijaykrishnan, Xueqing Li, Kaisheng Ma, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

Effect of Power Optimizations on Soft Error Rate

Narayanan Vijaykrishnan, Mary Jane Irwin, Yuan Xie, 2003, VLSI-SoC.

Memory system energy: Influence of hardware-software optimizations

Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut Kandemir, 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

Dual Mode Ferroelectric Transistor based Non-Volatile Flip-Flops for Intermittently-Powered Systems

Narayanan Vijaykrishnan, Arnab Raha, Vijay Raghunathan, 2018, ISLPED.

Masking the energy behaviour of encryption algorithms

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2003 .

Hardware and software techniques for DRAM energy management

Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut Kandemir, 2001 .

Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs

V. Kamakoti, Narayanan Vijaykrishnan, Vikram Chandrasekhar, 2005, ASP-DAC.

Techniques for Designing Energy-Aware MPSoCs

Luca Benini, Narayanan Vijaykrishnan, Mary Jane Irwin, 2005 .

Compiler support for reducing leakage energy consumption

Wei Zhang, Mahmut T. Kandemir, Narayanan Vijaykrishnan, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

CCC: crossbar connected caches for reducing energy consumption of on-chip multiprocessors

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2003, Euromicro Symposium on Digital System Design, 2003. Proceedings..

Energy optimization techniques in cluster interconnects

Mahmut T. Kandemir, Chita R. Das, Narayanan Vijaykrishnan, 2003, ISLPED '03.

SHARC: A streaming model for FPGA accelerators and its application to Saliency

Narayanan Vijaykrishnan, Srinidhi Kestur, Dharav Dantara, 2011, 2011 Design, Automation & Test in Europe.

RAFT: A router architecture with frequency tuning for on-chip networks

Chita R. Das, Narayanan Vijaykrishnan, Reetuparna Das, 2011, J. Parallel Distributed Comput..

A clock power model to evaluate impact of architectural and technology optimizations - a summary

Narayanan Vijaykrishnan, Mary Jane Irwin, D. E. Duarte, 2003 .

Reducing dynamic and leakage energy in VLIW architectures

Wei Zhang, Mahmut T. Kandemir, Narayanan Vijaykrishnan, 2006, TECS.

Towards Energy-Aware Iteration Space Tiling

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2000, LCTES.

Object duplication for improving reliability

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2006, Asia and South Pacific Conference on Design Automation, 2006..

FPGA-accelerator system for computing biologically inspired feature extraction models

Narayanan Vijaykrishnan, Chaitali Chakrabarti, Chi-Li Yu, 2011, 2011 Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR).

Tunnel FET-based ultra-low power, high-sensitivity UHF RFID rectifier

Narayanan Vijaykrishnan, Suman Datta, Huichu Liu, 2013, International Symposium on Low Power Electronics and Design (ISLPED).

A hybrid SoC interconnect with dynamic TDMA-based transaction-less buses and on-chip networks

Chita R. Das, Narayanan Vijaykrishnan, Yuan Xie, 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

Power-aware partitioned cache architectures

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2001, ISLPED '01.

FeFET-based low-power bitwise logic-in-memory with direct write-back and data-adaptive dynamic sensing interface

Narayanan Vijaykrishnan, Yu Wang, Huazhong Yang, 2020, ISLPED.

Tunnel FET technology: A reliability perspective

Narayanan Vijaykrishnan, Suman Datta, Huichu Liu, 2014, Microelectron. Reliab..

A criticality-driven microarchitectural three dimensional (3D) floorplanner

Narayanan Vijaykrishnan, Yuan Xie, Guangyu Sun, 2009, 2009 Asia and South Pacific Design Automation Conference.

On the Effects of Process Variation in Network-on-Chip Architectures

Chita R. Das, Narayanan Vijaykrishnan, Mary Jane Irwin, 2010, IEEE Transactions on Dependable and Secure Computing.

Leakage energy management in cache hierarchies

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2002, Proceedings.International Conference on Parallel Architectures and Compilation Techniques.

Technology-Assisted Computing-In-Memory Design for Matrix Multiplication Workloads

Narayanan Vijaykrishnan, Jack Sampson, Nicholas Jao, 2019, 2019 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

Area-Aware Decomposition for Single-Electron Transistor Arrays

Narayanan Vijaykrishnan, Suman Datta, Yung-Chih Chen, 2016, TODE.

PSB-RNN: A Processing-in-Memory Systolic Array Architecture using Block Circulant Matrices for Recurrent Neural Networks

Narayanan Vijaykrishnan, Jack Sampson, Sreenivas Subramoney, 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores

Narayanan Vijaykrishnan, Vinay Saripalli, Suman Datta, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

Improving Java performance using dynamic method migration on FPGAs

Luca Benini, Mahmut T. Kandemir, Narayanan Vijaykrishnan, 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..

Influence of leakage reduction techniques on delay/leakage uncertainty

Narayanan Vijaykrishnan, Mary Jane Irwin, Yuan Xie, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

Hotspot prevention through runtime reconfiguration in network-on-chip

Narayanan Vijaykrishnan, Greg M. Link, 2005, Design, Automation and Test in Europe.

Improving energy efficiency of multi-threaded applications using heterogeneous CMOS-TFET multicores

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Emre Kultursay, 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

Using complete system simulation to characterize SPECjvm98 benchmarks

Narayanan Vijaykrishnan, Anand Sivasubramaniam, Lizy Kurian John, 2000, ICS '00.

Energy and performance considerations in work partitioning for mobile spatial queries

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2003, Proceedings International Parallel and Distributed Processing Symposium.

A streaming FPGA implementation of a steerable filter for real-time applications (abstract only)

Narayanan Vijaykrishnan, Srinidhi Kestur, Dharav Dantara, 2011, FPGA '11.

Comparing Energy, Area, Delay Tradeoffs in Going Vertical with CMOS and Asymmetric HTFETs

Narayanan Vijaykrishnan, Jack Sampson, Moon Seok Kim, 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.

Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design

Narayanan Vijaykrishnan, Jaydeep P. Kulkarni, Vinay Saripalli, 2011, 2011 IEEE/ACM International Symposium on Nanoscale Architectures.

High performance array processor for video decoding

Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, 2005, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05).

Online detection and diagnosis of multiple configuration upsets in LUTs of SRAM-based FPGAs

V. Kamakoti, Narayanan Vijaykrishnan, Vikram Chandrasekhar, 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

X-VS: Crossbar-Based Processing-in-Memory Architecture for Video Summarization

Narayanan Vijaykrishnan, Nagadastagiri Challapalle, Sahithi Rampalli, 2020, 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Formulation and validation of an energy dissipation model for the clock generation circuitry and distribution networks

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.

Process Variation Aware Parallelization Strategies for MPSoCs

Narayanan Vijaykrishnan, Suresh Srinivasan, Raghavan Ramadoss, 2006, 2006 IEEE International SOC Conference.

Thermal trends in emerging technologies

Narayanan Vijaykrishnan, Greg M. Link, N. Vijaykrishnan, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

Low-leakage robust SRAM cell design for sub-100nm technologies

Narayanan Vijaykrishnan, Yuan Xie, Wenping Wang, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Scheduling reusable instructions for power reduction

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Exploring architectural heterogeneity in intelligent vision systems

Luca Benini, Narayanan Vijaykrishnan, Antonio Pullini, 2015, 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA).

A VLSI array architecture with dynamic frequency clocking

Narayanan Vijaykrishnan, N. Ranganathan, N. Bhavanishankar, 1996, Proceedings International Conference on Computer Design. VLSI in Computers and Processors.

Data driven adaptation for QoS aware embedded vision systems

Narayanan Vijaykrishnan, Jack Sampson, Kevin M. Irick, 2014, 2014 IEEE Global Conference on Signal and Information Processing (GlobalSIP).

Design of power-aware FPGA fabrics

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Aman Gayasen, 2007, Int. J. Embed. Syst..

Exploring architectural solutions for energy optimisations in bus-based system-on-chip

Luca Benini, Narayanan Vijaykrishnan, Federico Angiolini, 2008, IET Comput. Digit. Tech..

Nonvolatile Processor Architectures: Efficient, Reliable Progress with Unstable Power

Narayanan Vijaykrishnan, Yuan Xie, Xueqing Li, 2016, IEEE Micro.

EMERALD: Characterization of emerging applications and algorithms for low-power devices

Rob A. Rutenbar, Narayanan Vijaykrishnan, Mei Chen, 2013, 2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

A Distributed Multi-Point Network Interface for Low-Latency, Deadlock-Free On-Chip Interconnects

Chita R. Das, Narayanan Vijaykrishnan, Jongman Kim, 2006, 2006 1st International Conference on Nano-Networks and Workshops.

FPGA Architecture for 2D Discrete Fourier Transform Based on 2D Decomposition for Large-sized Data

Narayanan Vijaykrishnan, Chaitali Chakrabarti, Chi-Li Yu, 2009, 2009 IEEE Workshop on Signal Processing Systems.

Multidimensional DFT IP Generator for FPGA Platforms

Narayanan Vijaykrishnan, Chi-Li Yu, Kevin M. Irick, 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

A Unified Streaming Architecture for Real Time Face Detection and Gender Classification

Narayanan Vijaykrishnan, Hankyu Moon, Rajeev Sharma, 2007, 2007 International Conference on Field Programmable Logic and Applications.

Designing leakage aware multipliers

Narayanan Vijaykrishnan, Mary Jane Irwin, M. DeRenzo, 2004, 17th International Conference on VLSI Design. Proceedings..

Dynamic Power and Energy Management for Energy Harvesting Nonvolatile Processor Systems

Narayanan Vijaykrishnan, Yuan Xie, Xueqing Li, 2017, ACM Trans. Embed. Comput. Syst..

Soft error and energy consumption interactions: a data cache perspective

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

Characterization of memory energy behavior

Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut Kandemir, 2001 .

CAPE: A Content-Addressable Processing Engine

Narayanan Vijaykrishnan, Khalid Al-Hawaj, Christopher Batten, 2021, 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA).

Transformer-based Machine Learning for Fast SAT Solvers and Logic Synthesis pdf

Narayanan Vijaykrishnan, Song-Chun Zhu, Feng Shi, 2021, ArXiv.

Design space for scaling-in general purpose computing within the DDR DRAM hierarchy for map-reduce workloads

Narayanan Vijaykrishnan, Anand Sivasubramaniam, Prasanna Venkatesh Rengasamy, 2021, CF.

Ferroelectric-based Accelerators for Computationally Hard Problems

Narayanan Vijaykrishnan, Nikhil Shukla, Chonghan Lee, 2021, ACM Great Lakes Symposium on VLSI.

Resolution-Aware Deep Multi-View Camera Systems

Narayanan Vijaykrishnan, Zeinab Hakimi, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Microprocessor at 50: Industry Leaders Speak

Narayanan Vijaykrishnan, Lizy Kurian John, N. Vijaykrishnan, 2021, IEEE Micro.

Gesture-SNN: Co-optimizing accuracy, latency and energy of SNNs for neuromorphic vision sensors

Chita R. Das, Narayanan Vijaykrishnan, Abhronil Sengupta, 2021, 2021 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

The 4th Artificial Intelligence of Things (AIoT) Workshop

Narayanan Vijaykrishnan, Yiran Chen, Paramvir Bahl, 2021, KDD.

Microprocessor at 50: A Time to Celebrate and Energize for the Future

Narayanan Vijaykrishnan, Lizy Kurian John, 2021, IEEE Micro.

Overview of Ferroelectric Memory Devices and Reliability Aware Design Optimization

Narayanan Vijaykrishnan, Kai Ni, Shan Deng, 2021, ACM Great Lakes Symposium on VLSI.

Sparse to Dense Depth Completion using a Generative Adversarial Network with Intelligent Sampling Strategies

Narayanan Vijaykrishnan, Siddharth Advani, Nelson Daniel Troncoso Aldas, 2021, ACM Multimedia.

MaxTracker: Continuously Tracking the Maximum Computation Progress for Energy Harvesting ReRAM-based CNN Accelerators

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Keni Qiu, 2021, ACM Trans. Embed. Comput. Syst..

FPRA: A Fine-grained Parallel RRAM Architecture

Narayanan Vijaykrishnan, Rachata Ausavarungnirun, Tajana Simunic, 2021, 2021 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

Hardware Functional Obfuscation With Ferroelectric Active Interconnects pdf

Narayanan Vijaykrishnan, Sven Beyer, Stefan Dünkel, 2021, ArXiv.

Origin: Enabling On-Device Intelligence for Human Activity Recognition Using Energy Harvesting Wireless Sensor Networks

Narayanan Vijaykrishnan, Jack Sampson, Cyan Subhra Mishra, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Trends and Opportunities for SRAM Based In-Memory and Near-Memory Computation

Narayanan Vijaykrishnan, Ravi Iyer, Tanay Karnik, 2021, 2021 22nd International Symposium on Quality Electronic Design (ISQED).

An Oscillator-based MaxSAT solver pdf

Narayanan Vijaykrishnan, Nikhil Shukla, Chonghan Lee, 2021, ArXiv.

Exploiting Activation based Gradient Output Sparsity to Accelerate Backpropagation in CNNs pdf

Chita R. Das, Narayanan Vijaykrishnan, Asit K. Mishra, 2021, ArXiv.

SLAT : Secure Localization with Attack Tolerance

Narayanan Vijaykrishnan, Patrick McDaniel, Matthew Pirretti, 2005 .

Energy Behavior of Java Applications from the Memory Perspective

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2001, Java Virtual Machine Research and Technology Symposium.