A. Greiner

发表

A generic architecture for on-chip packet-switched interconnections

P. Guerrier, A. Greiner, 2000, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537).

Accurate static timing analysis for deep submicronic CMOS circuits

Alain Greiner, Karim Dioury, Marie-Minerve Rosset-Louërat, 1997 .

Use of Multi-Phase Stability Intervals to handle Crosstalk with the Timing Analyzer

A. Greiner, G. Avot, MM. Louërat, 2002 .

RAPID-2, an object-oriented associative memory applicable to genome data processing

Alain Greiner, Pascal Faudemay, Denis Archambaud, 1994, 1994 Proceedings of the Twenty-Seventh Hawaii International Conference on System Sciences.

The influence of system calls and interrupts on the performance of a PC cluster using a remote DMA communication primitive

Alain Greiner, Jean-Luc Lamotte, Olivier Glück, 2002 .

Protocol and performance analysis of the MPC parallel computer

Alain Greiner, Olivier Glück, Amal Zerrouki, 2001, Proceedings 15th International Parallel and Distributed Processing Symposium. IPDPS 2001.

THE MPC PARALLEL COMPUTER : HARDWARE, LOW-LEVEL PROTOCOLS AND PERFORMANCES

Alain Greiner, Amal Zerrouki, Olivier Gluck, 2000 .

IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management

Christian Bernard, Fabien Clermidy, Alain Greiner, 2021, IEEE Journal of Solid-State Circuits.

A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip

Alain Greiner, Zhen Zhang, Sami Taktak, 2008, 2008 45th ACM/IEEE Design Automation Conference.

A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach

Alain Greiner, Ivan Miro Panades, Abbas Sheibanyrad, 2006, 2006 1st International Conference on Nano-Networks and Workshops.

On Cache Coherency and Memory Consistency Issues in NoC Based Shared Memory Multiprocessor SoC Architectures

Alain Greiner, Frédéric Pétrot, Pascal Gomez, 2006, 9th EUROMICRO Conference on Digital System Design (DSD'06).

NoC-MPU: A secure architecture for flexible co-hosting on shared memory MPSoCs

Alain Greiner, Christian Schwarz, Joel Porquet, 2011, 2011 Design, Automation & Test in Europe.

Multi-compartment: A new architecture for secure co-hosting on SoC

A. Greiner, J. Porquet, C. Schwarz, 2009, 2009 International Symposium on System-on-Chip.

Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures

Alain Greiner, Ivan Miro Panades, A. Greiner, 2007, First International Symposium on Networks-on-Chip (NOCS'07).

Systematic Comparison between the Asynchronous and the Multi-Synchronous Implementations of a Network on Chip Architecture

Alain Greiner, Ivan Miro Panades, Abbas Sheibanyrad, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

An Efficient TLM/T Modeling and Simulation Environment Based on Conservative Parallel Discrete Event Principles

Alain Greiner, François Pêcheux, Emmanuel Viaud, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Using C to write portable CMOS VLSI module generators

Alain Greiner, Frédéric Pétrot, A. Greiner, 1994, EURO-DAC '94.

Designing portable module generators using the Alliance CAD system

A. Greiner, F. Petrot, A. Greiner, 1994, Proceedings of 26th Southeastern Symposium on System Theory.

Application of a redefinable symbolic simulation technique in VLSI testability design rules checking

Alain Greiner, Mokhtar Hirech, El Housseine Rejouan, 1994, 27th Annual Simulation Symposium.

Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture

Fabien Clermidy, Alain Greiner, Ivan Miro Panades, 2008, Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008).

Cycle precise core based hardware/software system simulation with predictable event propagation

Alain Greiner, Frédéric Pétrot, Denis Hommais, 1997, EUROMICRO 97. Proceedings of the 23rd EUROMICRO Conference: New Frontiers of Information Technology (Cat. No.97TB100167).

2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters

Christian Bernard, Fabien Clermidy, Alain Greiner, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

Multisynchronous and Fully Asynchronous NoCs for GALS Architectures

Alain Greiner, Ivan Miro Panades, Abbas Sheibanyrad, 2008, IEEE Design & Test of Computers.

Physical design of the VCI wrappers for the on-chip packet-switched network named SPIN

Alain Greiner, Adrijean Andriahantenaina, Hervé Charlery, 2004, Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004..

A simulation environment for core based embedded systems

Alain Greiner, Frédéric Pétrot, Denis Hommais, 1997, Proceedings of 1997 SCS Simulation Multiconference.

A Portable Clock Multiplier Generator using Digital CMOS Standard Cells

Alain Greiner, Karim Dioury, Michel Combes, 1995, ESSCIRC '95: Twenty-first European Solid-State Circuits Conference.

Micro-network for SoC: implementation of a 32-port SPIN network

Alain Greiner, Adrijean Andriahantenaina, A. Greiner, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Design methodology of a test chip for a portable 8ns 10 ports register file

A. Greiner, L. Lucas, A. Greiner, 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.