Houxiang Ji

Pinned loads: taming speculative loads in secure processors

J. Torrellas, D. Marinov, Z. Zhao, 2022, ASPLOS.

Graphite

Christopher W. Fletcher, J. Torrellas, Houxiang Ji, 2022, Proceedings of the 49th Annual International Symposium on Computer Architecture.

Graphite: optimizing graph neural networks on CPUs through cooperative software-hardware techniques

Christopher W. Fletcher, C. Hughes, J. Torrellas, 2022, ISCA.

SAVE: Sparsity-Aware Vector Engine for Accelerating DNN Training and Inference on CPUs

Josep Torrellas, Christopher J. Hughes, Christopher W. Fletcher, 2020, 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

SparseTrain: Leveraging Dynamic Sparsity in Software for Training DNNs on General-Purpose SIMD Processors

Christopher W. Fletcher, C. Hughes, J. Torrellas, 2019, PACT.

ReCom: An efficient resistive accelerator for compressed deep neural networks

Yiran Chen, Hai Li, Li Jiang, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Comparative Reasoning for Knowledge Graph Fact Checking

Jiejun Xu, Houxiang Ji, H. Tong, 2022, 2022 IEEE International Conference on Big Data (Big Data).

SparseTrain: Leveraging Dynamic Sparsity in Training DNNs on General-Purpose SIMD Processors pdf

Josep Torrellas, Christopher W. Fletcher, Houxiang Ji, 2019, ArXiv.

HUBPA: High Utilization Bidirectional Pipeline Architecture for Neuromorphic Computing

Li Jiang, Naifeng Jing, Xiaoyao Liang, 2019, 2019 24th Asia and South Pacific Design Automation Conference (ASP-DAC).