Raghavan Kumar

发表

Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS

Sanu Mathew, Vikram Suresh, Mark Anders, 2020, 2020 IEEE Symposium on VLSI Circuits.

PHAP: Password based Hardware Authentication using PUFs

Wayne P. Burleson, Raghavan Kumar, 2012, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture Workshops.

A 4900×m2 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2019, 2019 Symposium on VLSI Circuits.

A 617 TOPS/W All Digital Binary Neural Network Accelerator in 10nm FinFET CMOS

Himanshu Kaul, Amit Agarwal, Gregory K. Chen, 2020, 2020 IEEE Symposium on VLSI Circuits.

A 9.0-TOPS/W Hash-Based Deep Neural Network Accelerator Enabling 128× Model Compression in 10-nm FinFET CMOS

Himanshu Kaul, Amit Agarwal, Gregory K. Chen, 2020, IEEE Solid-State Circuits Letters.

On design of a highly secure PUF based on non-linear current mirrors

Wayne P. Burleson, Raghavan Kumar, W. Burleson, 2014, 2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

Physically Unclonable Functions: A Window into CMOS Process Variations

Wayne Burleson, Toshiaki Kirihata, Raghavan Kumar, 2016 .

Side-Channel Assisted Modeling Attacks on Feed-Forward Arbiter PUFs Using Silicon Data

Wayne P. Burleson, Raghavan Kumar, W. Burleson, 2015, RFIDSec.

A 225-950mV 1.5Tbps/W Whirlpool Hashing Accelerator for Secure Automotive Platforms in 14nm CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2019, 2019 IEEE Custom Integrated Circuits Conference (CICC).

Precise fault-injections using voltage and temperature manipulation for differential cryptanalysis

Ilia Polian, Philipp Jovanovic, Raghavan Kumar, 2014, 2014 IEEE 20th International On-Line Testing Symposium (IOLTS).

Hybrid modeling attacks on current-based PUFs

Wayne P. Burleson, Raghavan Kumar, 2014, 2014 IEEE 32nd International Conference on Computer Design (ICCD).

A 2.9–33.0 TOPS/W Reconfigurable 1-D/2-D Compute-Near-Memory Inference Accelerator in 10-nm FinFET CMOS

Himanshu Kaul, Amit Agarwal, Gregory K. Chen, 2020, IEEE Solid-State Circuits Letters.

A 4096-Neuron 1M-Synapse 3.8PJ/SOP Spiking Neural Network with On-Chip STDP Learning and Sparse Weights in 10NM FinFET CMOS

Gregory K. Chen, Ram Krishnamurthy, Raghavan Kumar, 2018, 2018 IEEE Symposium on VLSI Circuits.

25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs

Gregory K. Chen, Ram Krishnamurthy, Aravind Dasu, 2019, 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Program phase duration prediction and its application to fine-grain power management

Sandip Kundu, Sudarshan Srinivasan, Raghavan Kumar, 2013, 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power AOI Clocked Circuits in 14nm CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2019, 2019 Symposium on VLSI Circuits.

Active and Passive Side-Channel Attacks on Delay Based PUF Designs

Georg T. Becker, Raghavan Kumar, G. Becker, 2014, IACR Cryptol. ePrint Arch..

A 220-900mV 179Mcode/s 36pJ/code Canonical Huffman Encoder for DEFLATE Compression in 14nm CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2019, 2019 IEEE Custom Integrated Circuits Conference (CICC).

25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range

Vikram Suresh, Himanshu Kaul, Amit Agarwal, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

Evaluating and Enhancing Intel® Stratix® 10 FPGAs for Persistent Real-Time AI

Gregory K. Chen, Ram Krishnamurthy, Aravind Dasu, 2019, FPGA.

On improving reliability of delay based Physically Unclonable Functions under temperature variations

Sandip Kundu, Raghavan Kumar, Harikrishnan Chandrikakutty, 2011, 2011 IEEE International Symposium on Hardware-Oriented Security and Trust.

A SCA-Resistant AES Engine in 14nm CMOS with Time/Frequency-Domain Leakage Suppression using Non-Linear Digital LDO Cascaded with Arithmetic Countermeasures

Sanu Mathew, Vikram Suresh, Mark Anders, 2020, 2020 IEEE Symposium on VLSI Circuits.

Post-Silicon Validation and Calibration of Hardware Security Primitives

Wayne P. Burleson, Xiaolin Xu, Vikram B. Suresh, 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

Threat Analysis, Countermeaures and Design Strategies for Secure Computation in Nanometer CMOS Regime

Raghavan Kumar, Raghavan Kumar, 2015 .

Neuromorphic circuits for storing and generating connectivity information

Gregory K. Chen, Ram Krishnamurthy, Raghavan Kumar, 2016 .

A 54% Power-Saving Static Fully-Interruptible Single-Phase-Clocked Shared-Keeper Flip-Flop in 14nm CMOS

Sanu Mathew, Vikram Suresh, Mark Anders, 2019, 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC).

On Design of Low Cost Power Supply Noise Detection Sensor for Microprocessors

Sandip Kundu, Raghavan Kumar, Arunkumar Vijayakumar, 2012, 2012 IEEE Computer Society Annual Symposium on VLSI.

Cryogenic SiGe integrated circuits for superconducting nanowire single photon detector readout

Giovanni Resta, Matthew D. Shaw, Damon Russell, 2014, Sensing Technologies + Applications.

A 4900- $\mu$ m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition

Sudhir Satpathy, Vikram Suresh, Himanshu Kaul, 2020, IEEE Journal of Solid-State Circuits.

A 1.4GHz 20.5Gbps GZIP decompression accelerator in 14nm CMOS featuring dual-path out-of-order speculative Huffman decoder and multi-write enabled register file array

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2019, 2019 Symposium on VLSI Circuits.

A 0.26% BER, 1028 Challenge-Response Machine-Learning Resistant Strong-PUF in 14nm CMOS Featuring Stability-Aware Adversarial Challenge Selection

Sanu Mathew, Vikram Suresh, Mark Anders, 2020, 2020 IEEE Symposium on VLSI Circuits.

An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS

Vikram Suresh, Himanshu Kaul, Amit Agarwal, 2019, IEEE Journal of Solid-State Circuits.

Litho-aware and low power design of a secure current-based physically unclonable function

Wayne P. Burleson, Raghavan Kumar, 2013, International Symposium on Low Power Electronics and Design (ISLPED).

Design of Unique and Reliable Physically Unclonable Functions Based on Current Starved Inverter Chain

Sandip Kundu, Vinay C. Patil, Raghavan Kumar, 2011, 2011 IEEE Computer Society Annual Symposium on VLSI.

Protecting cryptographic hardware against malicious attacks by nonlinear robust codes

Yaara Neumeier, Osnat Keren, Ilia Polian, 2014, 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

A 435MHz, 2.5Mbps/W Side-Channel-Attack Resistant Crypto-Processor for Secure RSA-4K Public-Key Encryption in 14nm CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2020, 2020 IEEE Symposium on VLSI Circuits.

A Ray-Casting Accelerator in 10nm CMOS for Efficient 3D Scene Reconstruction in Edge Robotics and Augmented Reality Applications

Mark Anders, Himanshu Kaul, Amit Agarwal, 2020, 2020 IEEE Symposium on VLSI Circuits.

A 4096-Neuron 1M-Synapse 3.8-pJ/SOP Spiking Neural Network With On-Chip STDP Learning and Sparse Weights in 10-nm FinFET CMOS

Gregory K. Chen, Raghavan Kumar, H. Ekin Sumbul, 2019, IEEE Journal of Solid-State Circuits.

A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm CMOS Featuring Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2019, 2019 Symposium on VLSI Circuits.

Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware

Wayne P. Burleson, Ilia Polian, Philipp Jovanovic, 2014, 2014 Workshop on Fault Diagnosis and Tolerance in Cryptography.

On Design of Temperature Invariant Physically Unclonable Functions Based on Ring Oscillators

Sandip Kundu, Vinay C. Patil, Raghavan Kumar, 2012, 2012 IEEE Computer Society Annual Symposium on VLSI.

On Manufacturing Aware Physical Design to Improve the Uniqueness of Silicon-Based Physically Unclonable Functions

Sandip Kundu, Raghavan Kumar, Siva Nishok Dhanuskodi, 2014, 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems.

A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS

Himanshu Kaul, Amit Agarwal, Gregory K. Chen, 2021, IEEE Journal of Solid-State Circuits.

When the Physical Disorder of CMOS Meets Machine Learning

Xiaolin Xu, Wayne Burleson, Shuo Li, 2018 .

A system-level solution for managing spatial temperature gradients in thinned 3D ICs

Sandip Kundu, Raghavan Kumar, Arunachalam Annamalai, 2013, International Symposium on Quality Electronic Design (ISQED).

INVITED: A 0.26% BER, Machine-Learning Resistant 1028 Challenge-Response PUF in 14nm CMOS Featuring Stability-Aware Adversarial Challenge Selection

Sanu Mathew, Raghavan Kumar, Vikram B. Suresh, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).