Yi-Jong Yeh

An Optimization-Based Multiple-Voltage Scaling Technique for Low-Power CMOS Digital Design

Yi-Jong Yeh, Sy-Yen Kuo, S. Kuo, 2002, J. Circuits Syst. Comput..

An optimization-based low-power voltage scaling technique using multiple supply voltages

Yi-Jong Yeh, Sy-Yen Kuo, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

ASimulation-Based Temporal Assertion Checker forPSL

Yi-Jong Yeh, Kai-Hui Chang, Wei-Ting Tu, 2004 .

A Temporal Assertion Extension to Verilog

Yi-Jong Yeh, Sy-Yen Kuo, Kai-Hui Chang, 2004, ATVA.

Automatic Partitioner for Behavior Level Distributed Logic Simulation

Yi-Jong Yeh, Sy-Yen Kuo, Kai-Hui Chang, 2005, FORTE.

A simulation-based temporal assertion checker for PSL

Yi-Jong Yeh, Sy-Yen Kuo, Kai-Hui Chang, 2003, 2003 46th Midwest Symposium on Circuits and Systems.

Converter-free multiple-voltage scaling techniques for low-powerCMOS digital design

Yi-Jong Yeh, Sy-Yen Kuo, Jing-Yang Jou, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

SYSTEM LEVEL ASSERTION-BASED VERIFICATION ENVIRONMENT FOR PCI/PCI-X AND PCI-EXPRESS

Yi-Jong Yeh, Sy-Yen Kuo, Kai-Hui Chang, 2004 .