Y. Seo

A 2 GHz Fractional-N Digital PLL with 1b Noise Shaping $\Delta\Sigma$ TDC

J. Sim, Hong-June Park, Dong-Woo Jee, 2012, IEEE Journal of Solid-State Circuits.

A 0.63ps resolution, 11b pipeline TDC in 0.13µm CMOS

Hong-June Park, Jun-Seok Kim, Jae-Yoon Sim, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

23.2 A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme

Hankyu Chi, Dongkyun Kim, Changhyun Lee, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices

Hyun-Soo Park, Hyuk-Jun Kwon, Jong-Ho Lee, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking

Yong Jae Lee, Hyun-Soo Park, Hyuk-Jun Kwon, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18 $\mu$ m CMOS

Jae-Yoon Sim, Hong-June Park, Seon-Kyoo Lee, 2010, IEEE Journal of Solid-State Circuits.

A 300-MS/s, 1.76-ps-Resolution, 10-b Asynchronous Pipelined Time-to-Digital Converter With on-Chip Digital Background Calibration in 0.13-µm CMOS

Jae-Yoon Sim, Hong-June Park, Yunjae Suh, 2013, IEEE Journal of Solid-State Circuits.