S. Rylov

An adaptively-pipelined mixed synchronous-asynchronous digital FIR filter chip operating at 1.3 GigaHertz

M. Singh, J.A. Tierno, A. Rylyakov, 2010, Proceedings Eighth International Symposium on Asynchronous Circuits and Systems.

A 10Gb/s eye-opening monitor in 0.13 /spl mu/m CMOS

A. Rylyakov, A. Hajimiri, S. Rylov, 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

A 1.3 GSample/s 10-tap full-rate variable-latency self-timed FIR filter with clocked interfaces

A. Rylyakov, J. Tierno, S. Rylov, 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

A 10-Gb/s two-dimensional eye-opening monitor in 0.13-/spl mu/m standard CMOS

A. Rylyakov, A. Hajimiri, S. Rylov, 2005, IEEE Journal of Solid-State Circuits.