M. Kang

3nm GAA Technology featuring Multi-Bridge-Channel FET for Low Power and High Performance Applications

S. Jung, D. Kim, K. Bhuwalka, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

A 45nm low power system-on-chip technology with dual gate (logic and I/O) high-k/metal gate strained silicon transistors

P. Bai, N. Lindert, K. Mistry, 2008, 2008 IEEE International Electron Devices Meeting.

RF CMOS technology scaling in High-k/metal gate era for RF SoC (system-on-chip) applications

J. Rizk, K. Soumyanath, P. VanDerVoorn, 2010, 2010 International Electron Devices Meeting.

A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications

G. Curello, W. Hafez, M. Kang, 2012, 2012 International Electron Devices Meeting.

PRAM Technology: from Non Volatility to High Performances

H. Horii, D. Ahn, C. Chung, 2010 .