Y. Sherazi

Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology

D. Yakimets, D. Jang, A. Spessot, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

The Complementary FET (CFET) for CMOS scaling beyond N3

G. Bouche, J. Ryckaert, D. Mocuta, 2018, 2018 IEEE Symposium on VLSI Technology.

Device-, Circuit- & Block-level evaluation of CFET in a 4 track library

D. Yakimets, P. Matagne, D. Jang, 2019, 2019 Symposium on VLSI Technology.

Extreme scaling enabled by 5 tracks cells: Holistic design-device co-optimization for FinFETs and lateral nanowires

J. Ryckaert, D. Verkest, M. Badaroglu, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

The impact of sequential-3D integration on semiconductor scaling roadmap

B. Parvais, A. Vandooren, J. Ryckaert, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

IMEC N7, N5 and beyond: DTCO, STCO and EUV insertion strategy to maintain affordable scaling trend

Diederik Verkest, Kurt G. Ronse, Jae Uk Lee, 2018, Advanced Lithography.

Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7

Wim Dehaene, Praveen Raghavan, Pieter Weckx, 2017, 2017 47th European Solid-State Device Research Conference (ESSDERC).

Dedicated technology threshold voltage tuning for 6T SRAM beyond N7

Wim Dehaene, Praveen Raghavan, Pieter Weckx, 2017, 2017 IEEE International Conference on IC Design and Technology (ICICDT).

Power-performance Trade-offs for Lateral NanoSheets on Ultra-Scaled Standard Cells

B. Parvais, D. Verkest, Y. Sherazi, 2018, 2018 IEEE Symposium on VLSI Technology.

Semi-damascene Integration of a 2-layer MOL VHV Scaling Booster to Enable 4-track Standard Cells

D. Tsvetanova, N. Horiguchi, J. Ryckaert, 2022, International Electron Devices Meeting.