Kazuyoshi Takagi

发表

Rapid Single-Flux-Quantum Truncated Multiplier Based on Bit-Level Processing

Nobutaka Kito, Ryota Odaka, Kazuyoshi Takagi, 2019, IEICE Trans. Electron..

Automatic Wire-Routing of SFQ Digital Circuits Considering Wire-Length Matching

Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi, 2016, IEEE Transactions on Applied Superconductivity.

A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing

Kazuyoshi Takagi, Kazuhiro Nakamura, Naofumi Takagi, 2010, IEICE Trans. Inf. Syst..

Conversion of a CMOS Logic Circuit Design to an RSFQ Design Considering Latching Function of RSFQ Logic Gates

Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi, 2015, IEEE Transactions on Applied Superconductivity.

A Fast Algorithm for Multiplicative Inversion in GF(2m) Using Normal Basis

Kazuyoshi Takagi, Naofumi Takagi, Jun-ichi Yoshiki, 2001, IEEE Trans. Computers.

A VLSI Architecture for Output Probability and Likelihood Score Computations of HMM-Based Recognition Systems

Kazuyoshi Takagi, Kazuhiro Nakamura, Naofumi Takagi, 2012 .

Multi-Terminal Routing with Length-Matching for Rapid Single Flux Quantum Circuits

Kazuyoshi Takagi, Tsung-Yi Ho, Pei-Yi Cheng, 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing

Kazuyoshi Takagi, Kazuhiro Nakamura, Naofumi Takagi, 2010 .

Design concept of a lightweight runtime environment for robot software components onto embedded devices: work-in-progress

Kazuyoshi Takagi, Tomoya Mori, Naofumi Takagi, 2018, EMSOFT.

Design and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Floating-Point Multipliers Using a 10kA/cm2 Nb Process

Kazuyoshi Takagi, Yuki Yamanashi, Nobuyuki Yoshikawa, 2014, IEICE Trans. Electron..

Logic simulation tool for RSFQ circuits accepting arrivals of multiple pulses in a clock period

Nobutaka Kito, Kazuyoshi Takagi, Shohei Udatsu, 2020 .

Minimum Cut Linear Arrangement of p-q Dags for VLSI Layout of Adder Trees

Kazuyoshi Takagi, Naofumi Takagi, 1999 .

C-8-12 Demonstration of SFQ Microprocessor data path to the Tornado Architecture

Kazuyoshi Takagi, Yoshiaki Takai, Yuki Yamanashi, 2006 .

Design and Analysis of VLSI Circuits Based on Directed Acyclic Graphs

Kazuyoshi Takagi, 1999 .

DS-1-7 Computational Complexity of Arithmetic Operations on a Circuit Model Considering Wire Delay

Kazuyoshi Takagi, Naofumi Takagi, Tetsuya Nagase, 2009 .

A Memory Efficient Scalable VLSI Architecture for Output Probability Computations of HMM-based Recognition Systems

Kazuyoshi Takagi, Kazuhiro Nakamura, Naofumi Takagi, 2004 .

Exact Minimization of Free BDDs and Its Application to Pass-Transistor Logic Optimization (Special Section on VLSI Design and CAD Algorithms)

Kazuyoshi Takagi, Katsumasa Watanabe, Shinji Kimura, 1999 .

Work-in-Progress: Design Concept of a Lightweight Runtime Environment for Robot Software Components Onto Embedded Devices

Kazuyoshi Takagi, Tomoya Mori, Naofumi Takagi, 2018, 2018 International Conference on Embedded Software (EMSOFT).

An Operation Scenario Model for Energy Harvesting Embedded Systems and an Algorithm to Maximize the Operation Quality

Atsushi Iwata, Kazuyoshi Takagi, Naofumi Takagi, 2014, 2014 IEEE Intl Conf on High Performance Computing and Communications, 2014 IEEE 6th Intl Symp on Cyberspace Safety and Security, 2014 IEEE 11th Intl Conf on Embedded Software and Syst (HPCC,CSS,ICESS).

80-GHz Operation of an 8-Bit RSFQ Arithmetic Logic Unit

Kazuyoshi Takagi, Naofumi Takagi, Masamitsu Tanaka, 2015, 2015 15th International Superconductive Electronics Conference (ISEC).

Logic Synthesis Method for Dual-Rail RSFQ Digital Circuits Using Root-Shared Binary Decision Diagrams

Kazuyoshi Takagi, Koji Obata, Naofumi Takagi, 2007, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Waiting false path analysis of sequential logic circuits for performance optimization

Kazuyoshi Takagi, Katsumasa Watanabe, Shinji Kimura, 1998, ICCAD.

C-8-10 A High-Throughput SFQ Bit-Serial Floating-Point Multiplier Based on Systolic Architecture

Kazuyoshi Takagi, Koji Obata, Naofumi Takagi, 2007 .

A Hardware Algorithm for Integer Division Using the SD2 Representation

Kazuyoshi Takagi, Naofumi Takagi, Shunsuke Kadowaki, 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A hardware algorithm for integer division

Kazuyoshi Takagi, Naofumi Takagi, Shunsuke Kadowaki, 2005, 17th IEEE Symposium on Computer Arithmetic (ARITH'05).

Development of Multiplier and Divider IPs

Kazuyoshi Takagi, Naofumi Takagi, Masayuki Shinohara, 2002 .

Foreword: Special section on VLSI design and CAD algorithms

Yuichiro Shibata, Makoto Ikeda, Hiroyuki Tomiyama, 2014 .

A VLSI Architecture with Multiple Fast Store-Based Block Parallel Processing for Output Probability and Likelihood Score Computations in HMM-Based Isolated Word Recognition

Kazuyoshi Takagi, Kazuhiro Nakamura, Naofumi Takagi, 2012, IEICE Trans. Electron..

Development of Bit-Serial RSFQ Microprocessors Integrated with Shift-Register-Based Random Access Memories

Kazuyoshi Takagi, Naofumi Takagi, Nobuyuki Yoshikawa, 2015, 2015 15th International Superconductive Electronics Conference (ISEC).

An Allocation Optimization Method for Partially-reliable Scratch-pad Memory in Embedded Systems

Kazuyoshi Takagi, Naofumi Takagi, Hideki Takase, 2015, IPSJ Trans. Syst. LSI Des. Methodol..

Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis

Kazuyoshi Takagi, Naofumi Takagi, Hideki Takase, 2014, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

mROS: A Lightweight Runtime Environment for Robot Software Components onto Embedded Devices

Kazuyoshi Takagi, Tomoya Mori, Naofumi Takagi, 2019, HEART 2019.

VLSI CAD Education and Exercise Course with Public Domain Tools

Masahiro Fujita, Kunihiro Asada, Kazuyoshi Takagi, 2007, 2007 IEEE International Conference on Microelectronic Systems Education (MSE'07).

A Fast Wire-Routing Method and an Automatic Layout Tool for RSFQ Digital Circuits Considering Wire-Length Matching

Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi, 2018, IEEE Transactions on Applied Superconductivity.

An evaluation framework of OS-level power managements for the big.LITTLE architecture

Kazuyoshi Takagi, Yutaka Matsubara, Naofumi Takagi, 2016, 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS).

High-Throughput Rapid Single-Flux-Quantum Circuit Implementations for Exponential and Logarithm Computation Using the Radix-2 Signed-Digit Representation

Kazuyoshi Takagi, Naofumi Takagi, Masamitsu Tanaka, 2016, IEICE Trans. Electron..

A VLSI Architecture of Parallel Hough Transform with Localized Voting Space Access

Kazuyoshi Takagi, Kazuhiro Nakamura, Naofumi Takagi, 2008 .

High-Speed Operation of Random-Access-Memory-Embedded Microprocessor With Minimal Instruction Set Architecture Based on Rapid Single-Flux-Quantum Logic

Kazuyoshi Takagi, Naofumi Takagi, Yuki Hatanaka, 2017, IEEE Transactions on Applied Superconductivity.

Digit-recurrence algorithm for computing reciprocal square-root

Kazuyoshi Takagi, Daisuke Matsuoka, Naofumi Takagi, 2003 .

An allocation optimization method for partially-reliable instruction scratch-pad memory in embedded systems

Kazuyoshi Takagi, Naofumi Takagi, Hideki Takase, 2014, 2014 International SoC Design Conference (ISOCC).

Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits

Kazuyoshi Takagi, Yuki Ito, Naofumi Takagi, 2011, IEICE Trans. Electron..

Design and implementation of a pipelined 8 bit-serial single-flux-quantum microprocessor with cache memories

Kazuyoshi Takagi, Yuki Yamanashi, Nobuyuki Yoshikawa, 2007 .

Placement and Routing Methods Based on Mixed Wiring of JTLs and PTLs for RSFQ circuits

Kazuyoshi Takagi, Naofumi Takagi, Takashi Dejima, 2019, 2019 IEEE International Superconductive Electronics Conference (ISEC).

A Method of Sequential Circuit Synthesis Using One-Hot Encoding for Single-Flux-Quantum Digital Circuits

Kazuyoshi Takagi, Koji Obata, Naofumi Takagi, 2007, IEICE Trans. Electron..

Circuit Description and Design Flow of Superconducting SFQ Logic Circuits

Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi, 2014, IEICE Trans. Electron..

Buffer Construction Method for Nested Loops with Non-Uniform Dependencies in High-Level Synthesis

Kazuyoshi Takagi, Naofumi Takagi, Hideki Takase, 2013 .

Conversion Method of Netlists Consisting of Conventional Logic Gates to RSFQ Logic Circuits Utilizing Special RSFQ Gates

Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi, 2020, IEEE Transactions on Applied Superconductivity.

International Conference Report: Asia and South Pacific Design Automation Conference@@@Asia and South Pacific Design Automation Conference

Kazuyoshi Takagi, 2017 .

High-Speed Demonstration of Bit-Serial Floating-Point Adders and Multipliers Using Single-Flux-Quantum Circuits

Kazuyoshi Takagi, Naofumi Takagi, Yuki Yamanashi, 2015, IEEE Transactions on Applied Superconductivity.

Large-Scale Integrated Circuit Design Based on a Nb Nine-Layer Structure for Reconfigurable Data-Path Processors

Kazuyoshi Takagi, Nobuyuki Yoshikawa, Naofumi Takagi, 2014, IEICE Trans. Electron..

Demonstration of an 8-Bit SFQ Carry Look-Ahead Adder Using Clockless Logic Cells

Kazuyoshi Takagi, Naofumi Takagi, Masamitsu Tanaka, 2015, 2015 15th International Superconductive Electronics Conference (ISEC).

RSFQ 4-bit Bit-Slice Integer Multiplier

Kazuyoshi Takagi, Naofumi Takagi, Guang-Ming Tang, 2016, IEICE Trans. Electron..

Algorithms for Evaluating the Matrix Polynomial I+A+A2+...+AN-1 with Reduced Number of Matrix Multiplications

Kazuyoshi Takagi, Naofumi Takagi, Kotaro Matsumoto, 2018, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Clock Scheduling Algorithm for High-Throughput RSFQ Digital Circuits

Kazuyoshi Takagi, Koji Obata, Naofumi Takagi, 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

An Algorithm for Inversion in GF(2^m) Suitable for Implementation Using a Polynomial Multiply Instruction on GF(2)

Kazuyoshi Takagi, Naofumi Takagi, Katsuki Kobayashi, 2007, 18th IEEE Symposium on Computer Arithmetic (ARITH '07).

A 4-Bit Bit-Slice Multiplier for a 32-Bit RSFQ Microprocessor

Kazuyoshi Takagi, Naofumi Takagi, Guang-Ming Tang, 2015, 2015 15th International Superconductive Electronics Conference (ISEC).

A transduction-based framework to synthesize RSFQ circuits

Kazuyoshi Takagi, Koji Obata, Hideyuki Takada, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Design and Demonstration of an 8-bit Bit-Serial RSFQ Microprocessor: CORE e4

Kazuyoshi Takagi, Naofumi Takagi, Akira Fujimaki, 2016, IEEE Transactions on Applied Superconductivity.

Nb 9-Layer Fabrication Process for Superconducting Large-Scale SFQ Circuits and Its Process Evaluation

Kazuyoshi Takagi, Nobuyuki Yoshikawa, Naofumi Takagi, 2014, IEICE Trans. Electron..

A Buffering Method for Parallelized Loop with Non-Uniform Dependencies in High-Level Synthesis

Kazuyoshi Takagi, Naofumi Takagi, Hideki Takase, 2013, ICA3PP.

Automated Passive-Transmission-Line Routing Tool for Single-Flux-Quantum Circuits Based on A* Algorithm

Kazuyoshi Takagi, Koji Obata, Yuki Ito, 2010, IEICE Trans. Electron..

Low-Voltage Bit-Serial Single-Flux-Quantum Microprocessor for Integrating Memories

Kazuyoshi Takagi, Naofumi Takagi, Masamitsu Tanaka, 2015, 2015 15th International Superconductive Electronics Conference (ISEC).

Conversion of Logic Gates in Netlists for Rapid Single Flux Quantum Circuits Utilizing Confluence of Pulses

Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi, 2019, IPSJ Trans. Syst. LSI Des. Methodol..

Timing Verification of Sequential Logic Circuits Based on Controlled Multi-Clock Path Analysis (Special Section on VLSI Design and CAD Algorithms)

Kazuyoshi Takagi, Katsumasa Watanabe, Shinji Kimura, 1998 .

mROS: A Lightweight Runtime Environment of ROS 1 nodes for Embedded Devices

Kazuyoshi Takagi, Naofumi Takagi, Hideki Takase, 2020, J. Inf. Process..

Design Method of Dual-Rail RSFQ Logic Circuits Using 2×2-Join

Kazuyoshi Takagi, Koji Obata, Naofumi Takagi, 2005 .

A Verification Method for Single-Flux-Quantum Circuits Using Delay-Based Time Frame Model

Kazuyoshi Takagi, Takahiro Kawaguchi, Naofumi Takagi, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

An application specific Java processor with reconfigurabilities

Kazuyoshi Takagi, Katsumasa Watanabe, Shinji Kimura, 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

Hardware Synthesis from C Programs with Estimation of Bit Length of Variables

Kazuyoshi Takagi, Katsumasa Watanabe, Shinji Kimura, 1999 .

Splitter-Aware Multi-Terminal Routing with Length Matching Constraint for RSFQ Circuits

Kazuyoshi Takagi, Tsung-Yi Ho, Pei-Yi Cheng, 2020 .

A Layout Design Flow for RSFQ Circuits Based on Cell Clustering and Mixed Wiring of JTLs and PTLs

Kazuyoshi Takagi, Naofumi Takagi, Takashi Dejima, 2020, IEEE Transactions on Applied Superconductivity.

An application specific Java processor with reconfigurabilities

Kazuyoshi Takagi, Katsumasa Watanabe, Shinji Kimura, 2000, ASP-DAC '00.

Conversion Method of Netlists Consisting of Conventional Logic Gates to RSFQ Logic Circuits Using the Characteristics of Pulse Logic

Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi, 2019, 2019 IEEE International Superconductive Electronics Conference (ISEC).

Timing-aware description methods and gate-level simulation of single flux quantum logic circuits

Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi, 2012 .

Fast and memory efficient VLSI architecture for output probability computations of HMM-based recognition systems

Kazuyoshi Takagi, Naofumi Takagi, Masatoshi Yamamoto, 2008, 2008 IEEE International Symposium on Circuits and Systems.

New Nb multi-layer fabrication process for large-scale SFQ circuits

Kazuyoshi Takagi, Nobuyuki Yoshikawa, Naofumi Takagi, 2009 .

A VLSI Algorithm for Division in GF(2m) Based on Extended Binary GCD Algorithm

Kazuyoshi Takagi, Naofumi Takagi, N. Takagi, 2002, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Computational Power of Nondeterministic Ordered Binary Decision Diagrams and Their Subclasses (Special Section on Discrete Mathematics and Its Applications)

Kazuyoshi Takagi, Shuzo Yajima, Yasuhiko Takenaga, 1997 .

Design of single flux quantum cells for a 10-Nb-layer process

Kazuyoshi Takagi, Yuki Yamanashi, Nobuyuki Yoshikawa, 2009 .