Hiroyuki Hara

发表

A 200 MHz 13 mm/sup 2/ 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme

Lee-Sup Kim, Takayasu Sakurai, M. Matsui, 1994 .

A Standard-Cell Based On-Chip NMOS and PMOS Performance Monitor for Process Variability Compensation

Yasuo Unekawa, Toshiyuki Yamagishi, Hiroyuki Hara, 2013, IEICE Trans. Electron..

A low-power multi-core media co-processor for mobile application processors

Shuou Nomura, Fumihiko Tachibana, Chen Kong Teh, 2009, 2009 IEEE International Conference on IC Design and Technology.

An area-efficient, standard-cell based on-chip NMOS and PMOS performance monitor for process variability compensation

Yasuo Unekawa, Toshiyuki Yamagishi, Hiroyuki Hara, 2012, 2012 IEEE COOL Chips XV.

MAC Bridging Schemes in a Global Networking Service Platform

Hideo Kitazume, Hiroyuki Hara, Junichi Murayama, 1997 .

Edge Node Design in a Global Networking Service Platform

Hideo Kitazume, Naoya Kukutsu, Hiroyuki Hara, 1997 .

A 250-MHz 256b-I/O 1-Mb STT-MRAM with advanced perpendicular MTJ based dual cell for nonvolatile magnetic caches to reduce active power of processors

Saori Kashiwada, Hiroki Noguchi, Shinobu Fujita, 2013, 2013 Symposium on VLSI Circuits.

An automated runtime power-gating scheme

Mototsugu Hamada, Yukihito Oowaki, Takeshi Kitahara, 2007, 2007 25th International Conference on Computer Design.

Designing a Core Control Message Protocol for a Grobal Networking Service Platform

Masaki Tanikawa, Junichi Murayama, Hideo Kitazume, 1998 .

Flexible microelectronics: New application for thin‐film transistors in fingerprint sensors

Tatsuya Shimoda, Simon Tam, Hiroyuki Hara, 2005 .

A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI

Makoto Takahashi, Mototsugu Hamada, Yukihito Oowaki, 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

Wireless and IP integrated system architectures for broadband mobile multimedia services

Junichi Murayama, Makoto Umeuchi, Masahiro Umehira, 1999, WCNC. 1999 IEEE Wireless Communications and Networking Conference (Cat. No.99TH8466).

Fault-Tolerance Control on Global Network Service Platform

Junichi Murayama, Hiroyuki Hara, Masaya Makino, 1999 .

7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture

Satoshi Takaya, Hiroki Noguchi, Shinobu Fujita, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

Designing an IP Intra-networking Architecture for a Global Networking Service Platform

Junichi Murayama, Naoya Kukutsu, Hiroyuki Hara, 1999 .

Pulse-Width Modulation with Current Uniformization for TFT-OLEDs

Daisuke Suzuki, Satoshi Inoue, Mutsumi Kimura, 2007, IEICE Trans. Electron..

A single-chip MPEG2 video decoder LSI

Kenji Maeguchi, Takayasu Sakurai, Hiroyuki Hara, 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

WP 4.6: 200MHz Video Compression Macrocells Using Low-Swing Differential Logic

Lee-Sup Kim, Yoshinori Watanabe, Takayasu Sakurai, 1992 .

A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40nm CMOS

Mototsugu Hamada, Chen Kong Teh, Hiroyuki Hara, 2011, 2011 IEEE International Solid-State Circuits Conference.

Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems

Mototsugu Hamada, Yukihito Oowaki, Chen Kong Teh, 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme

Hiroshi Nakamura, Satoshi Takaya, Hiroki Noguchi, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

Optimization of TWC Design for Various Engine Operation Conditions

Makoto Nagata, Hiroki Nakayama, Hiroyuki Hara, 2019 .

Interworking Schemes between Optical Access Networks and a Core Network in a Global Networking Service Platform

Junichi Murayama, Hideo Kitazume, Naoya Kukutsu, 1997 .

0.5W 3ns Register File and 0.6W 5ns 32kB Cache

Tadahiro Kuroda, Takayasu Sakurai, Hiroyuki Hara, 1991 .

Classification of Driving Methods for TFT-OLEDs and Novel Proposal Using Time Ratio Grayscale and Current Uniformization

Tatsuya Shimoda, Satoshi Inoue, Mutsumi Kimura, 2005, IEICE Trans. Electron..

A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm

Makoto Takahashi, Manabu Watanabe, Mototsugu Hamada, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

An IP Multicasting Architecture for a Global Networking Service Platform

Naoya Kukutsu, Hiroyuki Hara, Junichi Murakami, 1998 .

A process variation compensation scheme using cell-based forward body-biasing circuits usable for 1.2V design

Mototsugu Hamada, Yoshinori Watanabe, Shuou Nomura, 2008, 2008 IEEE Custom Integrated Circuits Conference.

A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM

Makoto Takahashi, Manabu Watanabe, Mototsugu Hamada, 2011, IEEE Journal of Solid-State Circuits.

Low-power design methodology for module-wise dynamic voltage and frequency scaling with dynamic de-skewing systems

Takeshi Kitahara, Hiroyuki Hara, Fumihiro Minami, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Cell-Attached Frame Encapsulation Schemes for a Global Networking Service Platform

Junichi Murayama, Hideo Kitazume, Naoya Kukutsu, 1997 .

A 0.8- mu m BiCMOS ATM switch on an 800 Mb/s asynchronous buffered banyan network

Sumio Tanaka, Kenji Maeguchi, Hiroyuki Hara, 1991 .

Special and Embedded Memory Macrocells for Low-Cost and Low-Power in MPEG Environment (Special Issue on ULSI Memory Technology)

Takayasu Sakurai, Hiroyuki Hara, Katsuhiro Seta, 1996 .

A 7uW deep-sleep, ultra low-power WLAN baseband LSI for mobile applications

Hirotsugu Kajihara, Yasuo Unekawa, Toshio Fujisawa, 2011, 2011 IEEE Cool Chips XIV.

A trimless, 0.5V–1.0V wide voltage operation, high density SRAM macro utilizing dynamic cell stability monitor and multiple memory cell access

Atsushi Kawasumi, Fumihiko Tachibana, Osamu Hirabayashi, 2011, IEEE Asian Solid-State Circuits Conference 2011.

Fabrication and Evaluation of the ECL/TTL Compatible BI-CMOS Gate Array

Yasuhiro Sugimoto, Hiroyuki Hara, Tsutomu Koyanagi, 1988 .

A bitline leakage compensation scheme for low-voltage SRAMs

Tadahiro Kuroda, Hiroyuki Hara, Toshinari Takayanagi, 2001, IEEE J. Solid State Circuits.