P. Sweany

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Building a Retargetable Compiler for Instruction-Level Parallel Architectures ∗

P. Sweany, 2006 .

Evaluating Register Bank Partitioning with Genetic Algorithms

S. Carr, P. Sweany, Dineel Sule, 2007 .

Hybrid Hardware / Software Synergism

P. Sweany, P. Burke, G. Albadarin, 2014 .

Scheduling Using Simulated Annealing

P. Sweany, 1998 .

Improving data cache performance with integrated use of split caches, victim cache and stream buffers

K. Kavi, P. Sweany, Afrin Naz, 2004, MEDEA '04.

Determination of Atmospheric Halocarbons by A Temperature-Programmed Gas Chromatographic Freezeout Concentration Method

J. Krasnec, R. Rasmussen, P. Sweany, 1977 .

An Experimental Evaluation of the Sufficiency of Scalar Replacement Algorithms

Philip H. Sweany, Steve Carr, Qunyan Wu, 2007 .

An experimental evaluation of scalar replacement on scientific benchmarks

Philip H. Sweany, Steve Carr, S. Carr, 2003, Softw. Pract. Exp..

Optimizing loop performance for clustered VLIW architectures

Philip H. Sweany, Yi Qian, Steve Carr, 2002, Proceedings.International Conference on Parallel Architectures and Compilation Techniques.

Loop Transformations for Architectures with Partitioned Register Banks

Philip H. Sweany, Steve Carr, Xianglong Huang, 2001, OM '01.

Improving software pipelining with unroll-and-jam

Philip H. Sweany, Chen Ding, Steve Carr, 1996, Proceedings of HICSS-29: 29th Hawaii International Conference on System Sciences.

Building a retargetable local instruction scheduler

Philip H. Sweany, Bogong Su, Vicki H. Allan, 1998, Softw. Pract. Exp..

CRAIG: a practical framework for combining instruction scheduling and register assignment

Philip H. Sweany, Steve Carr, Thomas S. Brasier, 1995, PACT.

Inter-block code motion without copies

Philip H. Sweany, P. Sweany, 1992 .

Sampling of submitted papers

Steven Beaty, Philip Sweany, S. Beaty, 1990, SIGM.

Using Genetic Algorithms to Fine-Tune Instruction-Scheduling Heuristics

Philip H. Sweany, Steven J. Beaty, Scott Colcord, 1999 .

Trace scheduling optimization in a retargetable microcode compiler

Philip H. Sweany, Michael A. Howland, Robert A. Mueller, 1988, SIGM.

Trace scheduling optimization in a retargetable microcode compiler

Philip H. Sweany, Michael A. Howland, Robert A. Mueller, 1987, MICRO 20.

FPGA implementations of elliptic curve cryptography and Tate pairing over a binary field

Jian Huang, Philip H. Sweany, Dijiang Huang, 2008, J. Syst. Archit..

An FPGA implementation of elliptic curve cryptography for future secure web transaction

Jian Huang, Philip H. Sweany, Hao Li, 2007, PDCS.

Post-compaction register assignment in a retargetable compiler

Philip H. Sweany, Steven J. Beaty, S. Beaty, 1990, [1990] Proceedings of the 23rd Annual Workshop and Symposium@m_MICRO 23: Microprogramming and Microarchitecture.

Extending list scheduling to consider execution frequency

Philip H. Sweany, Steven J. Beaty, Michael J. Bourke, 1996, Proceedings of HICSS-29: 29th Hawaii International Conference on System Sciences.

Loop fusion for clustered VLIW architectures

Philip H. Sweany, Yi Qian, Steve Carr, 2002, LCTES/SCOPES '02.

Register assignment for software pipelining with partitioned register banks

Philip H. Sweany, Steve Carr, Jason Hiser, 2000, Proceedings 14th International Parallel and Distributed Processing Symposium. IPDPS 2000.

Improving software pipelining with hardware support for self-spatial loads

Philip H. Sweany, Steve Carr, S. Carr, 1999, CARN.

Modulo Scheduling with Cache Reuse Information

Philip H. Sweany, Chen Ding, Steve Carr, 1997, Euro-Par.

Improving Software Pipelining by Hiding Memory Latency with Combined Loads and Prefetches

Philip H. Sweany, Steve Carr, Soner Onder, 2001 .

Proceedings of the third international conference on Genetic algorithms

J. David Schaffer, R. A. Towle, Study, 1989 .

Automatic Code Generation Through Model-Driven Design

Philip H. Sweany, Patrick W. Burke, P. Sweany, 2007 .

Tiny split data-caches make big performance impact for embedded applications

Afrin Naz, Krishna M. Kavi, Wentong Li, 2006, J. Embed. Comput..

Improving data cache performance with integrated use of split caches, victim cache and stream buffers

K. Kavi, P. Sweany, Afrin Naz, 2005, MEDEA '04.

Speculative Thread Execution in a Multithreaded Dataflow Architecture

Afrin Naz, Krishna M. Kavi, Wentong Li, 2006, PDCS.

A Study of Separate Array and Scalar Caches

Afrin Naz, Krishna M. Kavi, Philip H. Sweany, 2004, HPCS.

Horizon: A Retargetable Compiler for Horizontal Microarchitectures

Philip H. Sweany, Robert A. Mueller, Michael R. Duda, 1988, IEEE Trans. Software Eng..

A Study of Reconfigurable Split Data Caches and Instruction Caches

Afrin Naz, Krishna M. Kavi, Wentong Li, 2006, PDCS.