R. Nebashi

发表

Low-current perpendicular domain wall motion cell for scalable high-speed MRAM

S. Fukami, Tetsuhiro Suzuki, N. Ishiwata, 2006, 2009 Symposium on VLSI Technology.

Soft-Delay-Error Evaluation in Content-Addressable Memory

Naoya Onizawa, Takahiro Hanyu, Shoun Matsunaga, 2014, 2014 IEEE 44th International Symposium on Multiple-Valued Logic.

High-speed Magnetic Memory based on Spin-Torque Domain Wall Motion

S. Fukami, Tetsuhiro Suzuki, N. Ishiwata, 2009 .

Robust Cu atom switch with over-400°C thermally tolerant polymer-solid electrolyte (TT-PSE) for nonvolatile programmable logic

N. Banno, M. Tada, T. Sakamoto, 2016, 2016 IEEE Symposium on VLSI Technology.

Pathway to Atomic-Switch Based Programmable Logic

Toshitsugu Sakamoto, Yukihide Tsuji, Munehiro Tada, 2020 .

Analysis of MTJ Edge Deformation Influence on Switching Current Distribution for Next-Generation High-Speed MRAMs

S. Miura, H. Honjo, S. Saito, 2009, IEEE Transactions on Magnetics.

Performance of write-line inserted magnetic tunneling junction for low-write-current magnetic random access memory cell

S. Fukami, Tetsuhiro Suzuki, N. Ishiwata, 2008 .

Growth and characterization of 28Sin/30Sin isotope superlattices

Y. Shiraki, K. Itoh, T. Kojima, 2003 .

Plasma process induced physical damages on multilayered magnetic films for magnetic domain wall motion

H. Ohno, S. Ikeda, S. Fukami, 2014 .

Analysis of single-event upset of magnetic tunnel junction used in spintronic circuits caused by radiation-induced current

H. Ohno, T. Hanyu, M. Natsui, 2014 .

10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications

Tetsuo Endoh, Takahiro Hanyu, Hiroaki Honjo, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

Material Stack Design With High Tolerance to Process-Induced Damage in Domain Wall Motion Device

Hiroaki Honjo, Kunihiko Ishihara, Keizo Kinoshita, 2014, IEEE Transactions on Magnetics.

High-speed and reliable domain wall motion device: Material design for embedded memory and logic application

S. Fukami, S. Ikeda, N. Kasai, 2012, 2012 Symposium on VLSI Technology (VLSIT).

A 90nm 12ns 32Mb 2T1MTJ MRAM

Yuichi Ito, Hiroaki Honjo, Yosuke Kobayashi, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs

Ryusuke Nebashi, Noboru Sakimura, Tadahiko Sugibayashi, 2008, IEEE Journal of Solid-State Circuits.

A 4-Mb MRAM macro comprising shared write-selection transistor cells and using a leakage-replication read scheme

N. Kasai, N. Sakimura, T. Sugibayashi, 2007, 2007 IEEE Asian Solid-State Circuits Conference.

An atom-switch-based field-programmable gate array with optimized driving capability buffer

H. Hada, N. Banno, T. Sakamoto, 2019, Japanese Journal of Applied Physics.

Domain-wall-motion cell with perpendicular anisotropy wire and in-plane magnetic tunneling junctions

H. Ohno, S. Fukami, Tetsuhiro Suzuki, 2012 .

Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating

Daisuke Suzuki, Shoji Ikeda, Tetsuo Endoh, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

Fabrication of a 99%-energy-less nonvolatile multi-functional CAM chip using hierarchical power gating for a massively-parallel full-text-search engine

T. Endoh, S. Fukami, S. Ikeda, 2013, 2013 Symposium on VLSI Technology.

Spintronics primitive gate with high error correction efficiency 6(Perror)2 for logic-in memory architecture

T. Endoh, S. Fukami, N. Kasai, 2012, 2012 Symposium on VLSI Technology (VLSIT).

High-speed simulator including accurate MTJ models for spintronics integrated circuit design

Hiroki Koike, Tetsuo Endoh, Takahiro Hanyu, 2012, 2012 IEEE International Symposium on Circuits and Systems.

Three-terminal magnetic tunneling junction device with perpendicular anisotropy CoFeB sensing layer

Hiroaki Honjo, Kunihiko Ishihara, Keizo Kinoshita, 2014 .

A 500-MHz MRAM macro for high-performance SoCs

N. Sakimura, H. Honjo, S. Saito, 2008, 2008 IEEE Asian Solid-State Circuits Conference.

A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop

T. Endoh, T. Ohsawa, H. Koike, 2013, 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing

Tetsuo Endoh, Takahiro Hanyu, Hiroaki Honjo, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

NanoBridge-Based FPGA in High-Temperature Environments

Masayuki Inaba, Takuma Shirai, Toshitsugu Sakamoto, 2017, IEEE Micro.