S. Samudrala

CMOS implementation of a 32 b computer

R. Allmon, W. J. Bowhill, B. J. Benschneider, 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.

System, process, and design implications of a reduced supply voltage microprocessor

S. Samudrala, R. Allmon, J. Grodstein, 1990, 1990 37th IEEE International Conference on Solid-State Circuits.

A 50 MHz uniformly pipelined 64 b floating-point arithmetic processor

W. J. Bowhill, B. J. Benschneider, Elizabeth M. Cooper, 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.

A pipelined 50-MHz CMOS 64-bit floating-point arithmetic processor

W. J. Bowhill, B. J. Benschneider, M. N. Gavrielov, 1989 .

A 600MHz superscalar floating point processor

R. Allmon, S. Samudrala, B. Grundmann, 1998, Proceedings of the 24th European Solid-State Circuits Conference.