M. Togo

发表

High performance CMOS for GHz communication IC

H. Tezuka, T. Suzaki, A. Tanabe, 1996, 1996 Symposium on VLSI Technology. Digest of Technical Papers.

2.8-Gb/s 176-mW byte-interleaved and 3.0-Gb/s 118-mW bit-interleaved 8:1 multiplexers with a 0.15-/spl mu/m CMOS technology

T. Suzaki, M. Kaneko, A. Tanabe, 1996 .

Charge based DC compact modeling of bulk FinFET transistor

Cor Claeys, Antonio Cerdeira, Jacopo Franco, 2013 .

Newly Found Anomalous Gate Leakage Current (AGLC) for 65 nm Node and Beyond, and Its Countermeasure Using Nitrogen Implanted Poly-Si

T. Fukai, T. Watanabe, I. Yamamoto, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

64 Mb 6.8 ns random ROW access DRAM macro for ASICs

M. Togo, N. Nakamura, M. Hamada, 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

A salicide-bridged trench capacitor with a double-sacrificial-Si/sub 3/N/sub 4/-sidewall (DSS) for high-performance logic-embedded DRAMs

K. Yoshida, M. Togo, M. Hamada, 1997, International Electron Devices Meeting. IEDM Technical Digest.

Management of Power and Performance with Stress Memorization Technique for 45nm CMOS

H. Naruse, E. Morifuji, F. Matsuoka, 2007, 2007 IEEE Symposium on VLSI Technology.

AC performance improvement by RMG module for 14nm FinFETs and beyond

M. Togo, 2015 .

2.8 Gb/s 176 mW byte-interleaved and 3.0 Gb/s 118 mW bit-interleaved 8:1 multiplexers

K. Yoshida, T. Suzaki, M. Togo, 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

Ultrathin EOT high-κ/metal gate devices for future technologies: Challenges, achievements and perspectives (invited)

Tom Schram, T. Chiarella, M. Togo, 2011 .

Power-aware 65 nm node CMOS technology using variable V/sub DD/ and back-bias control with reliability consideration for back-bias mode

T. Fukai, M. Togo, K. Imai, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

Correlation Between the $V_{\rm th}$ Adjustment of nMOSFETs With HfSiO Gate Oxide and the Energy Profile of the Bulk Trap Density

R. Degraeve, B. Kaczer, N. Horiguchi, 2010, IEEE Electron Device Letters.

Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques

Naoto Horiguchi, Denis Shamiryan, Malgorzata Jurczak, 2011 .

Process-Dependent N/PBTI Characteristics of TiN Gate FinFETs

Byoung Hun Lee, L. Pantisano, T. Chiarella, 2012, IEEE Electron Device Letters.

Time-Dependent Dielectric Breakdown on Subnanometer EOT nMOS FinFETs

M. Togo, G. Groeseneken, T. Kauerauf, 2012, IEEE Transactions on Device and Materials Reliability.

Impact of recoiled-oxygen-free processing on 1.5 nm SiON gate-dielectric in sub-100 nm CMOS technology

M. Togo, T. Mogami, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

A 12 ns 8 MB DRAM secondary cache for a 64 b microprocessor

I. Naritake, M. Togo, T. Sugibayashi, 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

Plasma doping and reduced crystalline damage for conformally doped fin field effect transistors

Naoto Horiguchi, Aaron Thean, Guido Groeseneken, 2013 .

High-frequency characteristics and its dependence on parasitic components in 0.1 /spl mu/m Si-MOSFETs

A. Tanabe, M. Togo, A. Furukawa, 1996, 1996 Symposium on VLSI Technology. Digest of Technical Papers.

Multiple-thickness gate oxide and dual-gate technologies for high-performance logic-embedded DRAMs

M. Togo, K. Noda, T. Tanigawa, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

Ion-implantation-based low-cost Hk/MG process for CMOS low-power application

R. Degraeve, C. Ortolland, W. Vandervorst, 2010, 2010 Symposium on VLSI Technology.

A 12nm FinFET Technology Featuring 2nd Generation FinFET for Low Power and High Performance Applications

X. Wan, M. Togo, B. Zhu, 2018, 2018 IEEE Symposium on VLSI Technology.

A robust 65-nm node CMOS technology for wide-range Vdd operation

T. Fukai, T. Tamura, M. Togo, 2003, IEEE International Electron Devices Meeting 2003.

Electrical properties of 1.5-nm SiON gate-dielectric using radical oxygen and radical nitrogen

Tohru Mogami, Toru Tatsumi, M. Togo, 2002 .