O. Pollet

An Etch Stop and Sacrificial Materials Study for 3D NEMS-CMOS Co-Integration

T. Ernst, S. Hentz, J. Arcamone, 2014 .

ECD seed copper layer for seed enhancement in advanced interconnects

P. Haumesser, G. Passemard, T. Ritzdorf, 2003 .

Copper post-electroplating anneal: evaluation of in-line vs. furnace anneal on layer properties

S. Maitrejean, P. Haumesser, T. Mourier, 2003 .

Electroless deposition of CoWP: Material characterization and process optimization on 300mm wafers

A. Roule, P. Haumesser, G. Passemard, 2006 .

Stress optic modulator using thin-film PZT for LIDAR applications

S. Malhouitre, D. Fowler, W. Rabaud, 2019, 2019 IEEE SENSORS.

Thin layer etching of silicon nitride: A comprehensive study of selective removal using NH3/NF3 remote plasma

C. Arvet, N. Possémé, O. Pollet, 2016 .

Alternative process for thin layer etching: Application to nitride spacer etching stopping on silicon germanium

S. Barnola, Nicolas Posseme, Olivier Pollet, 2014 .

Understanding of a new approach for silicon nitride spacer etching using gaseous hydrofluoric acid after hydrogen ion implantation

S. Barnola, N. Possémé, N. Rochat, 2017 .

Etching and stripping process developments for sub-10nm FDSOI device architectures using alternative lithography techniques

S. Barnola, N. Possémé, O. Pollet, 2015, 2015 China Semiconductor Technology International Conference.