F. Hsueh

发表

Amorphous-Layer Regrowth and Activation of P and As Implanted Si by Low-Temperature Microwave Annealing

Yao-Jen Lee, T. Chao, Kun‐Lin Lin, 2011, IEEE Transactions on Electron Devices.

32-nm Multigate Si-nTFET With Microwave-Annealed Abrupt Junction

Yao-Jen Lee, T. Hou, F. Hou, 2016, IEEE Transactions on Electron Devices.

Comparisons on performance improvement by nitride capping layer among different channel directions nMOSFETs

Yao-Jen Lee, Horng-Chih Lin, Tiao-Yuan Huang, 2007, 2007 International Semiconductor Device Research Symposium.

A Novel Nanoinjection Lithography (NInL) Technology and Its Application for 16-nm Node Device Fabrication

C. Hu, Chun-Chi Chen, Jan-Tsai Liu, 2011, IEEE Transactions on Electron Devices.

DC and high-frequency characteristics of trigate polycrystalline-silicon thin-film transistors with different layout geometries

Kun-Ming Chen, G. Huang, C. Shen, 2019, Japanese Journal of Applied Physics.

3D 65nm CMOS with 320°C microwave dopant activation

J. M. Kowalski, Chia-Chen Wan, Yao-Jen Lee, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

High-Performance Uniaxial Tensile Strained n-Channel JL SOI FETs and Triangular JL Bulk FinFETs for Nanoscaled Applications

Yao-Jen Lee, F. Hou, P. Sung, 2017, IEEE Transactions on Electron Devices.

Fabrication of Vertically Stacked Nanosheet Junctionless Field-Effect Transistors and Applications for the CMOS and CFET Inverters

Yao-Jen Lee, C. Su, P. Sung, 2020, IEEE Transactions on Electron Devices.

Impacts of a buffer layer and hydrogen-annealed wafers on the performance of strained-channel nMOSFETs with SiN-capping layer

Yao-Jen Lee, T. Chao, Horng-Chih Lin, 2008 .

Analog and RF Characteristics of Power FinFET Transistors With Different Drain-Extension Designs

Kun-Ming Chen, G. Huang, Chun-Chi Chen, 2018, IEEE Transactions on Electron Devices.

Characterization of Ultra-Thin Ni Silicide Film by Two-Step Low Temperature Microwave Anneal

Yao-Jen Lee, P. Sung, T. Chao, 2014 .

Random Variation in Nanoscale HfZrO$_2$ Ferroelectric FinFETs: Physical Origin and Neuromorphic System Implications

Yao-Jen Lee, C. Su, P. Sung, 2020 .

Full low temperature microwave processed Ge CMOS achieving diffusion-less junction and Ultrathin 7.5nm Ni mono-germanide

Yao-Jen Lee, C. Hu, P. Sung, 2012, 2012 International Electron Devices Meeting.

Dopant Activation in Single-Crystalline Germanium by Low-Temperature Microwave Annealing

Yao-Jen Lee, T. Tseng, F. Hsueh, 2011, IEEE Electron Device Letters.

RF power FinFET transistors with a wide drain-extended fin

Kun-Ming Chen, G. Huang, Chun-Chi Chen, 2017 .

Low-Temperature Microwave Annealing Processes for Future IC Fabrication—A Review

Yao-Jen Lee, C. Hu, P. Sung, 2014, IEEE Transactions on Electron Devices.

Monolithic 3D SRAM-CIM Macro Fabricated with BEOL Gate-All-Around MOSFETs

Kun-Ming Chen, G. Huang, C. Hu, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Tri-Gate Ferroelectric FET Characterization and Modelling for Online Training of Neural Networks at Room Temperature and 233K

Sourav De, Yao-Jen Lee, Chun-Jung Su, 2020, 2020 Device Research Conference (DRC).

Monolithic 3D+-IC Based Massively Parallel Compute-in-Memory Macro for Accelerating Database and Machine Learning Primitives

Hariram Thirucherai Govindarajan, Srivatsa Srinivasa Rangachar, J. Sampson, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

High performance poly Si junctionless transistors with sub-5nm conformally doped layers by molecular monolayer doping and microwave incorporating CO2 laser annealing for 3D stacked ICs applications

G. Huang, Yao-Jen Lee, F. Hou, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrOx on specific interfacial layers exhibiting 65% S.S. reduction and improved ION

W.-F. Wu, C. Wang, C. Su, 2017, 2017 Symposium on VLSI Technology.

TSV-free FinFET-based Monolithic 3D+-IC with computing-in-memory SRAM cell for intelligent IoT devices

Guo-Wei Huang, Jia-Min Shieh, Chih-Chao Yang, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter

Yao-Jen Lee, C. Su, P. Sung, 2020, IEEE Journal of the Electron Devices Society.

Footprint-efficient and power-saving monolithic IoT 3D+ IC constructed by BEOL-compatible sub-10nm high aspect ratio (AR>7) single-grained Si FinFETs with record high Ion of 0.38 mA/μm and steep-swing of 65 mV/dec. and Ion/Ioff ratio of 8

Jia-Min Shieh, Chih-Chao Yang, Chang-Hong Shen, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Fluorescence signals of quantum dots influenced by spatially controlled array structures

Y. N. Chen, D. Chuu, C. Luo, 2009, Nanotechnology.

Observation of localized surface plasmons in spatially controlled array structures

D. Chuu, C. Luo, W. Chou, 2009, Nanotechnology.

A novel junctionless FinFET structure with sub-5nm shell doping profile by molecular monolayer doping and microwave annealing

P. Sung, K. Kao, Y. Lee, 2014, 2014 IEEE International Electron Devices Meeting.

Suspended Diamond-Shaped Nanowire With Four {111} Facets for High-Performance Ge Gate-All-Around FETs

Tuo-Hung Hou, Seiji Samukawa, Fu-Kuo Hsueh, 2016, IEEE Transactions on Electron Devices.

Diamond-shaped Ge and Ge0.9Si0.1 gate-all-around nanowire FETs with four {111} facets by dry etch technology

Guo-Wei Huang, Tuo-Hung Hou, Tien-Sheng Chao, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3-D Integration With Dual Work Function Gate for Ultralow-Power SRAM and RF Applications

J. Tarng, Kun-Ming Chen, G. Huang, 2022, IEEE Transactions on Electron Devices.

First Demonstration of Interface-Enhanced SAF Enabling 400°C-Robust 42 nm p-SOT-MTJ Cells with STT-Assisted Field-Free Switching and Composite Channels

C. Liu, Cho-Lun Hsu, D. Tang, 2021, 2021 Symposium on VLSI Technology.

A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support

Narayanan Vijaykrishnan, Meng-Fan Chang, Swaroop Ghosh, 2018, ISLPED.

First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications

C. Wang, C. Su, P. Sung, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

CiM3D: Comparator-in-Memory Designs Using Monolithic 3-D Technology for Accelerating Data-Intensive Applications

Jia-Min Shieh, Jack Sampson, Cheng-Xin Xue, 2021, IEEE Journal on Exploratory Solid-State Computational Devices and Circuits.

A Dual-Split-Controlled 4P2N 6T SRAM in Monolithic 3D-ICs With Enhanced Read Speed and Cell Stability for IoT Applications

Meng-Fan Chang, Guo-Wei Huang, Hiroyuki Yamauchi, 2018, IEEE Electron Device Letters.

Negative-Capacitance FinFET Inverter, Ring Oscillator, SRAM Cell, and Ft

Jia-Min Shieh, Chenming Hu, Wen-Cheng Chiu, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

Ultra-Low Power 3D NC-FinFET-based Monolithic 3D+ -IC with Computing-in-Memory for Intelligent IoT Devices

Guo-Wei Huang, Jia-Min Shieh, Chih-Chao Yang, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

First Demonstration of heterogenous Complementary FETs utilizing Low-Temperature (200 °C) Hetero-Layers Bonding Technique (LT-HBT)

H. J. Chen, J. Tarng, C. Su, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

Low-Temperature Microwave Annealing for MOSFETs With High-k/Metal Gate Stacks

Yao-Jen Lee, P. Sung, C. Luo, 2013, IEEE Electron Device Letters.

A 10 nm Si-based bulk FinFETs 6T SRAM with multiple fin heights technology for 25% better static noise margin

Chenming Hu, ChiaHua Ho, Yi-Ping Hsieh, 2013, 2013 Symposium on VLSI Technology.

A Low-Temperature Microwave Anneal Process for Boron-Doped Ultrathin Ge Epilayer on Si Substrate

J. M. Kowalski, G. Luo, Shih-Chiang Huang, 2009, IEEE Electron Device Letters.

Low temperature microwave annealed FinFETs with less Vth variability

P. Sung, Y. Lee, K. Endo, 2016, 2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Simulations of electric field distributions by the susceptor-coupling effects for 2.45GHz microwave inside microwave chamber

Yao-Jen Lee, T. Chao, F. Hsueh, 2015, 2015 IEEE 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits.

Low-temperature microwave annealing processes for future IC fabrication

Yao-Jen Lee, P. Sung, T. Chao, 2014, 2014 IEEE International Nanoelectronics Conference (INEC).

Susceptor Coupling for the Uniformity and Dopant Activation Efficiency in Implanted Si Under Fixed-Frequency Microwave Anneal

Yao-Jen Lee, T. Chao, F. Hsueh, 2012, IEEE Electron Device Letters.

High Tensile Stress with Minimal Dopant Diffusion by Low Temperature Microwave Anneal

Yao-Jen Lee, T. Chao, F. Hsueh, 2011 .

Low-cost and TSV-free monolithic 3D-IC with heterogeneous integration of logic, memory and sensor analogy circuitry for Internet of Things

Meng-Fan Chang, Guo-Wei Huang, Ting-Jen Hsueh, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

First Demonstration of Ultrafast Laser Annealed Monolithic 3D Gate-All-Around CMOS Logic and FeFET Memory with Near-Memory-Computing Macro

Kun-Ming Chen, G. Huang, C. Hu, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

Nanoscale p-MOS Thin-Film Transistor With TiN Gate Electrode Fabricated by Low-Temperature Microwave Dopant Activation

J. M. Kowalski, Yao-Jen Lee, T. Chao, 2010, IEEE Electron Device Letters.