C. L. Yang

发表

Process development of high-k metal gate aluminum CMP at 28nm technology node

J. Y. Wu, T. Tsai, Welch Lin, 2012 .

Characterization of Hf1-xZrxO2 Gate Dielectrics with 0≤x≤1 Prepared by Atomic Layer Deposition for Metal Oxide Semiconductor Field Effect Transistor Applications

C. C. Liu, Chien-Hung Wu, Shui-Jinn Wang, 2012 .

A Novel “hybrid” high-k/metal gate process for 28nm high performance CMOSFETs

C. H. Yu, G. H. Ma, C. L. Yang, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

A 28nm poly/SiON CMOS technology for low-power SoC applications

S. F. Tzou, Y. R. Wang, M. T. Chen, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Defect reduction of replacement metal gate aluminum chemical mechanical planarization at 28nm technology node

J. Y. Wu, Teng-Chun Tsai, Welch Lin, 2013 .

Investigation of the structural and electrical characterization on ZrO2 addition for ALD HfO2 with La2O3 capping layer integrated metal-oxide semiconductor capacitors

J. Y. Wu, C. C. Liu, S. J. Wang, 2011, 2011 IEEE/SEMI Advanced Semiconductor Manufacturing Conference.

A comparative study of gate stack material properties and reliability characterization in MOS transistors with optimal ALD Zirconia addition for hafina gate dielectric

J. Y. Wu, C. C. Liu, S. J. Wang, 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

Investigation of aluminum film properties and microstructure for replacement metal gate application

J. Y. Wu, M. Tsai, T. Tsai, 2013 .

Evaluation of aluminum film properties and microstructure for replacement metal gate application at 28nm technology node

J. Y. Wu, C. Hsu, M. Tsai, 2011, 2011 IEEE International Interconnect Technology Conference.

Effects of La2O3 Capping Layers Prepared by Different ALD Lanthanum Precursors on Flatband Voltage Tuning and EOT Scaling in TiN/HfO2/SiO2/Si MOS Structures

J. Y. Wu, C. C. Liu, Shui-Jinn Wang, 2011 .

Alleviating eSiGe Strain Relaxation Using Cryo-Implantation

C. I. Li, J. Y. Wu, B. Colombeau, 2011 .

Optimizing state-of-the-art 28nm core/SRAM device performance by cryo-implantation technology

T. Y. Lu, C. I. Li, Y. S. Huang, 2012, Proceedings of Technical Program of 2012 VLSI Technology, System and Application.

Mitigating eSiGe strain relaxation using cryo-implantation technology for PSD formation

C. I. Li, J. Y. Wu, I. Chen, 2011, 11th International Workshop on Junction Technology (IWJT).