J. Borrel

Detecting Unintended Schottky Junctions and Their Impact on Tunnel FET Characteristics

J. Hartmann, C. Tabone, M. Vinet, 2016, IEEE Transactions on Electron Devices.

Junction technology outlook for sub-28nm FDSOI CMOS

Laurent Grenouillet, Yves Morand, Maud Vinet, 2014, 2014 International Workshop on Junction Technology (IWJT).

PD-SOI CMOS and SiGe BiCMOS Technologies for 5G and 6G communications

P. Chevalier, O. Kermarrec, D. Gloria, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

Metal/Insulator/Semiconductor contacts for ultimately scaled CMOS nodes: Projected benefits and remaining challenges

H. Grampeix, E. Dubois, M. Vinet, 2016, 2016 16th International Workshop on Junction Technology (IWJT).

Ultra-thin dielectric insertions for contact resistivity lowering in advanced CMOS: Promises and challenges

E. Dubois, M. Vinet, L. Hutin, 2016 .

Composition of Carbon Clusters in Implanted Silicon Using Atom Probe Tomography

S. Duguay, D. Blavette, J. Borrel, 2021, Microscopy and Microanalysis.

450 GHz $f_{\text{T}}$ SiGe:C HBT Featuring an Implanted Collector in a 55-nm CMOS Node

P. Chevalier, C. Gaquiere, Michel Buczko, 2018, 2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS).

Considerations for efficient contact resistivity reduction via Fermi Level depinning - impact of MIS contacts on 10nm node nMOSFET DC characteristics

P. Batude, O. Rozeau, M. Vinet, 2015, Symposium on VLSI Technology.

Modeling of Fermi-Level Pinning Alleviation With MIS Contacts: n and pMOSFETs Cointegration Considerations—Part II

Maud Vinet, Emmanuel Dubois, Sebastien Martinie, 2016, IEEE Transactions on Electron Devices.

Modeling of Fermi-Level Pinning Alleviation With MIS Contacts: n and pMOSFETs Cointegration Considerations—Part I

E. Dubois, O. Rozeau, M. Vinet, 2016, IEEE Transactions on Electron Devices.