P. Larsson-Edefors

Bit-serial interleaved high speed division

William P. Marnane, S. J. Bellis, P. Larsson-Edefors, 1997 .

Interconnect Characterization Flow for Minimal-Segment Model Selection

P. Larsson-Edefors, D.A. Andersson, L.J. Svensson, 2006, 2006 NORCHIP.

VLSI implementation of CRC-32 for 10 Gigabit Ethernet

P. Larsson-Edefors, T. Henriksson, H. Eriksson, 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

A power cut-off technique for gate leakage suppression [CMOS logic circuits]

P. Larsson-Edefors, M. Drazdziulis, D. Eckerbert, 2004, Proceedings of the 30th European Solid-State Circuits Conference.

Toward a systematic sensitivity analysis of on-chip power grids using factor analysis

P. Larsson-Edefors, D.A. Andersson, L.J. Svensson, 2007, 2007 IEEE Workshop on Signal Propagation on Interconnects.

Dual threshold voltage circuits in the presence of resistive interconnects

P. Larsson-Edefors, L.J. Svensson, D. Eckerbert, 2003, IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings..

A 470-MHz CMOS true single-phase clocked bit-serial arithmetic unit

P. Larsson-Edefors, 1994 .

Cycle-true leakage current modeling for CMOS gates

P. Larsson-Edefors, D. Eckerbert, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

A gate leakage reduction strategy for future CMOS circuits

P. Larsson-Edefors, M. Drazdziulis, 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).

Most-significant-bit-first serial/parallel multipliers

William P. Marnane, P. Larsson-Edefors, 1998 .

Bit-serial, MSB first processing units

William P. Marnane, S. J. Bellis, P. Larsson-Edefors, 1999 .

A deep submicron power estimation methodology adaptable to variations between power characterization and estimation

P. Larsson-Edefors, D. Eckerbert, D. Eckerbert, 2003, Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003..