Jaydeep P. Kulkarni

发表

Memory and Logic soft error improvement using phase transition material assisted transistors

SS Teja Nibhanupudi, Amritesh Rai, Anupam Roy, 2018, 2018 4th IEEE International Conference on Emerging Electronics (ICEE).

High density NV-SRAM using memristor and selector as technology assist

Jaydeep P. Kulkarni, S.S. Teja Nibhanupudi, 2019, 2019 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

DL Tod Dickson Visits IEEE SSCS/CAS Central Texas Chapter [Chapters]

Jaydeep P. Kulkarni, 2019 .

An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS

Hong Wang, Deepak Mathaikutty, Sriram R. Vangal, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

VFAB: A Novel 2-Stage STTRAM Sensing Using Voltage Feedback and Boosting

Swaroop Ghosh, Jaydeep P. Kulkarni, Seyedhamidreza Motaman, 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

Device/circuit interactions at 22nm technology node

Kaushik Roy, Jaydeep P. Kulkarni, Sumeet Kumar Gupta, 2009, 2009 46th ACM/IEEE Design Automation Conference.

Report on the 2018 IEEE/ACM International Symposium on Low Power Electronics and Design

Thomas F. Wenisch, Jaydeep P. Kulkarni, 2018, IEEE Des. Test.

Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator

James Tschanz, Vivek De, Kaushik Mazumdar, 2016, IEEE Journal of Solid-State Circuits.

Chip Design 2020

Jaydeep P. Kulkarni, 2020, IEEE Micro.

A high sensitivity process variation sensor utilizing sub-threshold operation

Kaushik Roy, Franco Stellari, Peilin Song, 2008, 2008 IEEE Custom Integrated Circuits Conference.

A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM

Kaushik Roy, Jaydeep P. Kulkarni, Keejong Kim, 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory

Rolf Drechsler, Chip-Hong Chang, Chulwoo Kim, 2019, IEEE Trans. Very Large Scale Integr. Syst..

M2A2: Microscale Modular Assembled ASICs for High-Mix, Low-Volume, Heterogeneously Integrated Designs

Jaydeep P. Kulkarni, Aseem Sayal, Sidlgata V. Sreenivasan, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Jaydeep P. Kulkarni, Xueqing Li, Suman Datta, 2016, IEEE Transactions on Electron Devices.

Biomedical Circuits and Systems Best Paper Award

Massoud Pedram, Jaydeep P. Kulkarni, Kaushik Roy, 2015 .

Design for test and reliability in ultimate CMOS

Yervant Zorian, Nacer-Eddine Zergainoh, Lorena Anghel, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A Read-Disturb-Free, Differential Sensing 1R/1W Port, 8T Bitcell Array

Kaushik Roy, Patrick Ndai, Ashish Goel, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Fast LSF Search Algorithm Based on Interframe Correlation in G.723.1

Jaydeep P. Kulkarni, Sameer A. Kibey, Piyush D. Sarode, 2004, EURASIP J. Adv. Signal Process..

Editorial

Mark Mohammad Tehranipoor, Meng-Fan Chang, Rajiv V. Joshi, 2017, Formal Aspects of Computing.

Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design

Kaushik Roy, Jaydeep P. Kulkarni, K. Roy, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

IEEE SSCS DL Jae-Yoon Sim Visits SSCS Central Texas Chapter [Chapters]

Jaydeep P. Kulkarni, 2019 .

Thermal analysis of 8-T SRAM for nano-scaled technologies

Kaushik Roy, Jaydeep P. Kulkarni, Mesut Meterelliyoz, 2008, Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08).

Opportunities for PMOS read and write ports in low voltage dual-port 8T bit cell arrays

Vivek De, Jaydeep P. Kulkarni, Tanay Karnik, 2010, IEEE Custom Integrated Circuits Conference 2010.

Energy Efficient Volatile Memory Circuits for the IoT Era

Vivek De, Jaydeep P. Kulkarni, James W. Tschanz, 2017 .

Source-Underlapped GaSb–InAs TFETs With Applications to Gain Cell Embedded DRAMs

Jaydeep P. Kulkarni, Kaushik Roy, Ankit Sharma, 2016, IEEE Transactions on Electron Devices.

Process variation tolerant SRAM array for ultra low voltage applications

Kaushik Roy, Jaydeep P. Kulkarni, Sang Phill Park, 2008, 2008 45th ACM/IEEE Design Automation Conference.

5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep

Jaydeep P. Kulkarni, Charles Augustine, Arijit Raychowdhury, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

Neural Network Assisted Compact Model for Accurate Characterization of Cycle-to-cycle Variations in 2-D $h$-BN based RRAM devices

SS Teja Nibhanupudi, Jaydeep P. Kulkarni, Sanjay K. Banerjee, 2019, 2019 Device Research Conference (DRC).

Capacitive-coupling wordline boosting with self-induced VCC collapse for write VMIN reduction in 22-nm 8T SRAM

James Tschanz, Vivek De, Jaydeep P. Kulkarni, 2012, 2012 IEEE International Solid-State Circuits Conference.

Impact of Single Trap Random Telegraph Noise on Heterojunction TFET SRAM Stability

Jaydeep P. Kulkarni, Vinay Saripalli, Suman Datta, 2014, IEEE Electron Device Letters.

A novel slope detection technique for robust STTRAM sensing

Swaroop Ghosh, Jaydeep P. Kulkarni, Seyedhamidreza Motaman, 2015, 2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

Accurate characterization of random process variations using a robust low-voltage high-sensitivity sensor featuring replica-bias circuit

Kaushik Roy, Ashish Goel, Jaydeep P. Kulkarni, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating

James Tschanz, Vivek De, Jaydeep P. Kulkarni, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

IEEE SSCS DL Marvin Chang Visits IEEE SSCS/CAS Central Texas Chapter [Chapters]

Jaydeep P. Kulkarni, 2019 .

14.4 All-Digital Time-Domain CNN Engine Using Bidirectional Memory Delay Lines for Energy-Efficient Edge Computing

Jaydeep P. Kulkarni, Aseem Sayal, Shirin Fathima, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

4.7 A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging

Paolo A. Aseron, James Tschanz, Vivek De, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

Resilient design in scaled CMOS for energy efficiency

Keith A. Bowman, James Tschanz, Vivek De, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

Improving multi-core performance using mixed-cell cache architecture

Jaydeep P. Kulkarni, Samira Manabi Khan, Alaa R. Alameldeen, 2013, 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA).

A 409 GOPS/W Adaptive and Resilient Domino Register File in 22 nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging

Paolo A. Aseron, James Tschanz, Vivek De, 2016, IEEE Journal of Solid-State Circuits.

A 12.08-TOPS/W All-Digital Time-Domain CNN Engine Using Bi-Directional Memory Delay Lines for Energy Efficient Edge Computing

Jaydeep P. Kulkarni, Aseem Sayal, Shirin Fathima, 2020, IEEE Journal of Solid-State Circuits.

Analysis of SRAM and eDRAM Cache Memories Under Spatial Temperature Variations

Kaushik Roy, Jaydeep P. Kulkarni, Mesut Meterelliyoz, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction

Keith A. Bowman, James Tschanz, Vivek De, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

Impact of Process Variation on Self-Reference Sensing Scheme and Adaptive Current Modulation for Robust STTRAM Sensing

Swaroop Ghosh, Jaydeep P. Kulkarni, Seyedhamidreza Motaman, 2018, ACM J. Emerg. Technol. Comput. Syst..

Soft-FET: phase transition material assisted soft switching field effect transistor for supply voltage droop mitigation

Jaydeep P. Kulkarni, Subrahmanya Teja, 2018, DAC.

Dr. Mahesh Mehendale Visits the IEEE SSCS/CAS Central Texas Chapter [Chapters]

Jaydeep P. Kulkarni, 2019 .

8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation

James Tschanz, Vivek De, Kaushik Mazumdar, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

Message from the program co-chairs

Thomas F. Wenisch, Jaydeep P. Kulkarni, 2017, ISLPED.

Characterization of Random Process Variations Using Ultralow-Power, High-Sensitivity, Bias-Free Sub-Threshold Process Sensor

Kaushik Roy, Franco Stellari, Peilin Song, 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design

Narayanan Vijaykrishnan, Jaydeep P. Kulkarni, Vinay Saripalli, 2011, 2011 IEEE/ACM International Symposium on Nanoscale Architectures.

Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating

James Tschanz, Vivek De, Jaydeep P. Kulkarni, 2017, IEEE Journal of Solid-State Circuits.

Tri-Mode Independent Gate FinFET-Based SRAM With Pass-Gate Feedback: Technology–Circuit Co-Design for Enhanced Cell Stability

Jaydeep P. Kulkarni, Kaushik Roy, Sumeet Kumar Gupta, 2013, IEEE Transactions on Electron Devices.

A High Performance, Scalable Multiplexed Keeper Technique

Kaushik Roy, Jaydeep P. Kulkarni, K. Roy, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

A Low Power High Performance Multiplexed Keeper Technique

Kaushik Roy, Jaydeep P. Kulkarni, 2006 .

A 160 mV Robust Schmitt Trigger Based

Kaushik Roy, Jaydeep P. Kulkarni, Keejong Kim, 2007 .

REad/access-preferred (REAP) SRAM - architecture-aware bit cell design for improved yield and lower VMIN

Kaushik Roy, Patrick Ndai, Ashish Goel, 2009, 2009 IEEE Custom Integrated Circuits Conference.

Thermal-Aware Design Space Exploration of 3-D Systolic ML Accelerators

Jaydeep P. Kulkarni, Lizy John, Rahul Mathur, 2021, IEEE Journal on Exploratory Solid-State Computational Devices and Circuits.

An In-Memory-Computing Charge-Domain Ternary CNN Classifier

Nan Sun, David Z. Pan, Jaydeep P. Kulkarni, 2021, 2021 IEEE Custom Integrated Circuits Conference (CICC).

16.2 eDRAM-CIM: Compute-In-Memory Design with Reconfigurable Embedded-Dynamic-Memory Array Realizing Adaptive Data Converters and Charge-Domain Computing

Jaydeep P. Kulkarni, Pulkit Jain, Fatih Hamzaoglu, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

Realizing Direct Convolution in Memory with Systolic-RAM

Jaydeep P. Kulkarni, Jacob N. Rohan, 2021, 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC).

COMPAC: Compressed Time-Domain, Pooling-Aware Convolution CNN Engine With Reduced Data Movement for Energy-Efficient AI Computing

SS Teja Nibhanupudi, Jaydeep P. Kulkarni, Aseem Sayal, 2020, IEEE Journal of Solid-State Circuits.

A Systematic Evaluation of EM and Power Side-Channel Analysis Attacks on AES Implementations

Jaydeep P. Kulkarni, Vishnuvardhan V. Iyer, Meizhi Wang, 2021, 2021 IEEE International Conference on Intelligence and Security Informatics (ISI).

Galvanically Isolated, Power and Electromagnetic Side-Channel Attack Resilient Secure AES Core with Integrated Charge Pump based Power Management

Jaydeep P. Kulkarni, Michael Orshansky, Aseem Sayal, 2021, 2021 IEEE Custom Integrated Circuits Conference (CICC).

Field-Emission Enhanced Contacts for Disordered Semiconductor based Thin-Film Transistors

Jaydeep P. Kulkarni, Ananth Dodabalapur, Kelly Liang, 2021, 2021 Device Research Conference (DRC).

Physical Design Strategies for Mitigating Fine-Grained Electromagnetic Side-Channel Attacks

Sanu Mathew, Jaydeep P. Kulkarni, Michael Orshansky, 2021, 2021 IEEE Custom Integrated Circuits Conference (CICC).

Trends in Analog and Digital Intensive Compute-in-SRAM Designs

Jaydeep P. Kulkarni, Rishabh Sehgal, J. Kulkarni, 2021, 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS).

Compute-in-eDRAM with Backend Integrated Indium Gallium Zinc Oxide Transistors

Jaydeep P. Kulkarni, Shanshan Xie, Siddhartha Raman Sundara Raman, 2021, 2021 IEEE International Symposium on Circuits and Systems (ISCAS).