Ade Bekele

A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS

Elad Alon, Parag Upadhyaya, Ken Chang, 2012, 2012 Symposium on VLSI Circuits (VLSIC).

A O.96pJ/b 7 × 50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies

Kee Hian Tan, Yipeng Wang, P. Upadhyaya, 2023, 2023 IEEE International Solid- State Circuits Conference (ISSCC).

A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs

Ying Cao, Yohan Frans, Parag Upadhyaya, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

7 A 7 . 4to-14 GHz PLL with 54 fsrms Jitter in 16 nm FinFET for Integrated RF-Data-Converter SoCs

Yohan Frans, Parag Upadhyaya, Ken Chang, 2018 .

A 164fsrms 9-to-18GHz sampling phase detector based PLL with in-band noise suppression and robust frequency acquisition in 16nm FinFET

Mayank Raj, Yohan Frans, Parag Upadhyaya, 2017, 2017 Symposium on VLSI Circuits.